Florent Kermarrec
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0f46dc4ab7
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modules: add DDR3-800 timings for MT41J128M16 and use it on arty example
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2018-10-01 11:59:54 +02:00 |
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Florent Kermarrec
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426ae23d2a
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examples/litedram_gen: add sdram_module_speedgrade parameter
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2018-10-01 11:48:15 +02:00 |
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Florent Kermarrec
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30c32f557c
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example/litedram_gen: simplify clocking with new S7PLL module, a lot easier :)
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2018-09-25 10:40:24 +02:00 |
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Florent Kermarrec
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cc481be81f
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examples: add sdram_rank_nb and user_ports_id_width
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2018-09-07 17:55:46 +02:00 |
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Florent Kermarrec
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5e4dca9a7b
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add examples with standalone cores for arty and genesys2
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2018-08-31 23:20:47 +02:00 |