Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
1,455 Commits 5 Branches 14 Tags 5.7 MiB
Commit Graph

1455 Commits

Author SHA1 Message Date
Florent Kermarrec 4adfff2c8b modules: Add IS43TR16512B. 2021-09-30 15:44:14 +02:00
Florent Kermarrec 3afd617455 frontend/fifo: Simplify level on _LiteDRAMFIFOCtrl, fix ctrl.write on _LiteDRAMFIFOWriter. 2021-09-24 19:34:55 +02:00
Florent Kermarrec 9e9c83ce40 litedram_gen: Add Auto-Flush to UART in FIFO mode. 
In FIFO mode, backpressure is propagated to the UART and would stall the CPU
when the UART is not accepting data. Enable Auto-Flush on the UART to allow
DRAM initialization when the UART is not ready.
 2021-09-24 13:37:19 +02:00
Florent Kermarrec e52ece0b8a litedram_gen: Block accesses on User ports until the controller is successfully initialized. 
This is convenient on some systems to decouple DRAM accesses from the init status reported by
the cores. User ports can still try to write/read data to the ports, the controlled will
just block the transfers and release them when it will be initialized.
 2021-09-24 10:42:51 +02:00
Florent Kermarrec b24381ca4a frontend/fifo: Simplify code and expose pre/post fifo_depth instead of writer/reader_fifo_depth. 2021-09-24 09:52:24 +02:00
Florent Kermarrec 3d3bf623aa frontend/fifo: Simplify, fix corner cases. 2021-09-23 23:22:51 +02:00
Florent Kermarrec dd24073633 test/test_fifo: Use 4 x DRAM data-width in Bypass mode to use Pre/Post-Converter. 2021-09-23 18:57:00 +02:00
Florent Kermarrec d9ec9882af frontend_fifo: Fix dram_data_cnt signal size. 2021-09-23 18:56:09 +02:00
Florent Kermarrec 49cf76af84 litedram_gen: Fix/Cleanup #276 and #278. 2021-09-23 10:48:39 +02:00
enjoy-digital 6cfbaf80aa
Merge pull request #278 from ozbenh/fix-no-cpu-gen 
Fix generation with no CPU
 2021-09-23 10:42:20 +02:00
enjoy-digital f25247dd79
Merge pull request #276 from jfng/fix_gen_uart 
litedram_gen: Fix duplicate with_uart value when cpu_type is None.
 2021-09-23 10:42:01 +02:00
enjoy-digital 27e632f0d4
Merge pull request #275 from antmicro/acom/rdimm 
modules: add more RDIMM modules
 2021-09-23 10:41:21 +02:00
Alessandro Comodi f3cf9ba116 phy: s7: add DDR4 memtype as well 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-09-22 17:01:37 +02:00
Benjamin Herrenschmidt 4fdb9a2cf2 Fix generation with no CPU 
The various UART bits in there need to be skipped

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2021-09-22 21:01:56 +10:00
Florent Kermarrec 053434b9df litedram/gen/FIFO: Enable Bypass mode and do data-width adaptation directly in LiteDRAMFIFO. 2021-09-21 19:36:53 +02:00
Florent Kermarrec 2d4a47f260 frontend/fifo: Add initial optional/automatic Bypass implementation to LiteDRAMFIFO. 
Bypass will provide lower latency and configurable data-width.
 2021-09-21 19:23:36 +02:00
Jean-François Nguyen 9d8a0577e9 litedram_gen: Fix duplicate with_uart value when cpu_type is None. 2021-09-21 15:39:19 +02:00
Florent Kermarrec 43856dadd6 litedram_gen: Fix UART interrupt/polling. 2021-09-16 17:41:40 +02:00
Florent Kermarrec e0e204a514 litedram_gen: Add FIFO Mode to UART (and rename serial IOs to uart). 
It's more interesting in some design to access the UART through a FIFO like
interface than through RS232.
 2021-09-16 17:01:00 +02:00
Alessandro Comodi 1b8e1f0b88 modules: add more RDIMM modules 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-09-16 14:28:19 +02:00
Florent Kermarrec e9a4a746e9 CONTRIBUTORS: Update. 2021-09-15 14:43:09 +02:00
Florent Kermarrec 916f54e4f3 phy/s7ddrphy: Only add +1 to CL for DDR3 (thanks gsomlo). 2021-09-15 08:43:31 +02:00
Florent Kermarrec 6f323f6a7a phy/s7ddrphy: Add +1 to CL in MR register to increase sys_clk_freq range. 
Allow successful DDR3 calibration at lower sys_clk_freq (tested down to 50MHz).
 2021-09-14 16:33:33 +02:00
enjoy-digital 6a82042fee
Merge pull request #274 from teknoman117/alchitry-ram-modules 
Add AS4C128M16 DDR3L-1600 ram
 2021-09-09 11:53:42 +02:00
Nathaniel R. Lewis cbb699ce52 modules: add AS4C128M16 DDR3L module 2021-09-08 22:15:56 -07:00
Florent Kermarrec db879ae3f7 litedram_gen: Fix missing user_port request for FIFO ports. 2021-09-03 10:31:08 +02:00
Jędrzej Boczar d95212bf0b test: check converters at higher data width ratios 2021-09-01 14:59:05 +02:00
Jędrzej Boczar 220538b56f phy: add implementation for Etron RPC DRAM 2021-09-01 14:59:01 +02:00
enjoy-digital 80398a8a15
Merge pull request #269 from antmicro/jboc/dfi-converter-new 
DFI rate converter - 2nd attempt
 2021-08-23 19:34:10 +02:00
enjoy-digital ca609005bc
Merge pull request #268 from antmicro/jboc/init-refactor 
Refactor init code generation
 2021-08-23 18:51:51 +02:00
Jędrzej Boczar 86cde91987 phy: fix typo (read_level -> read_leveling) 2021-08-12 12:14:51 +02:00
enjoy-digital 203cc73ceb
Merge pull request #271 from antonblanchard/fix-sim 
litedram_gen: Fix error with --sim option
 2021-08-09 19:46:17 +02:00
Anton Blanchard fe1bb083ef litedram_gen: Fix error with --sim option 
It looks like commit 317072a198 ("litedram_gen: Add initial SDRAM
support (with ULX3S example)") broke building with the --sim option.
 2021-08-09 10:38:54 +10:00
enjoy-digital ae139096c0
Merge pull request #267 from antmicro/jboc/lpddr4-update 
LPDDR4 minor refactor
 2021-08-06 14:39:42 +02:00
Jędrzej Boczar f4be065c09 phy/s7ddrphy: add compatibility with DFIRateConverter 2021-08-04 12:30:56 +02:00
Jędrzej Boczar 46ea844702 phy: update PHYs to set capabilities, delays/bitslips in PhySettings 2021-08-04 12:30:56 +02:00
Jędrzej Boczar 1d880c4db9 phy/dfi: add automatic PHY wrapper generation for DFIRateConverter 2021-08-04 12:30:56 +02:00
Jędrzej Boczar 43036c9576 test: update *_init.h reference 2021-08-04 12:30:56 +02:00
Jędrzej Boczar 89af25a697 phy/utils: DFI rate converter for creating PHY wrappers at slower clocks 2021-08-04 12:30:56 +02:00
Jędrzej Boczar 377746bfd8 init: add helper class to make C code generation simpler 2021-08-04 12:30:56 +02:00
Jędrzej Boczar 2200bd43a5 test/reference: update headers to include SDRAM_PHY_DFI_DATABITS 2021-08-04 12:30:56 +02:00
Jędrzej Boczar 993ba31697 init: generate `#define SDRAM_PHY_DFI_DATABITS` constant 2021-08-04 12:30:56 +02:00
Jędrzej Boczar 91cae335e5 init: add parentheses around #define with an expression 2021-08-04 12:30:56 +02:00
Jędrzej Boczar d20e8c763b phy: move simulation related utilities to sim_utils.py 2021-08-04 10:20:45 +02:00
Jędrzej Boczar 1bd9455216 phy/lpddr4: update docstring 2021-08-04 10:20:45 +02:00
Florent Kermarrec 4326fe7f36 bench/kcu105/xcu1525: Also use PHYPadsReducer to easily test various DFI sizes. 2021-07-13 14:57:42 +02:00
Florent Kermarrec fd8d6f8334 phy/mode: Switch litedram.common imports to * to also import get_default_cl_cwl/get_sys_latency. 2021-07-09 18:52:34 +02:00
Florent Kermarrec 5a4ed3d204 bench/arty/kc705: Use PHYPadsReducer to easily test various DFI sizes. 2021-07-09 17:58:40 +02:00
Florent Kermarrec 894c7fb49e phy/model: Let the model pick default settings when settings is set to None (In this case, data_width needs to be provided). 2021-07-08 09:09:05 +02:00
Florent Kermarrec daf2cb7d39 phy/model: Integrate sdram_module_nphases/get_sdram_phy_settings from litex_sim. 2021-07-08 09:02:13 +02:00