Commit graph

1325 commits

Author SHA1 Message Date
Florent Kermarrec
5d7adcfa7c core/refresher: Add assert on clk_freq/tREFI ratio.
Prevent generating a controller with tREFI too low to accept any transaction.
2021-11-01 14:58:41 +01:00
Jean-François Nguyen
5aad6cd3d1 gen: use sys_clk_freq for SDRAMPHYModel timings, instead of 100MHz. 2021-11-01 14:28:19 +01:00
Florent Kermarrec
2b0f806c96 ci: Increase similarities with LiteX CI. 2021-10-26 12:15:39 +02:00
Florent Kermarrec
f537b5dd52 phy/s7ddrphy: Fix DDR2 case. 2021-10-18 15:33:56 +02:00
enjoy-digital
3202bc6acd
Merge pull request from antmicro/acom/s7phy_ddr4
phy: s7: add DDR4 memtype as well
2021-10-18 13:35:15 +02:00
Florent Kermarrec
1d5192f572 litedram_gen/fifo: Avoid unnecessary get_port(). 2021-10-08 08:52:50 +02:00
Florent Kermarrec
e1defa2687 litedram_gen: Fix rate for 7-Series. 2021-10-07 16:22:40 +02:00
Florent Kermarrec
1c59e77302 litedram_gen/add_sdram: Remove origin: no longer required. 2021-10-07 16:20:23 +02:00
Florent Kermarrec
f0a2f40a86 litedram_gen: Compute rate based on type of PHY (DDR3 rate is 1:2 with ECP5DDRPHY). 2021-10-07 15:41:51 +02:00
Florent Kermarrec
0bb3bff8af litedram_gen: Set default csr_data_width to 32 (similar to LiteX). 2021-10-07 15:28:36 +02:00
Florent Kermarrec
6b0a35b309 litedram_gen: Add rst signal to CRG and use it as PLL reset. 2021-10-07 14:00:53 +02:00
Florent Kermarrec
ba0012f881 examples/versa_ecp5: Fix memtype. 2021-10-07 13:44:36 +02:00
Florent Kermarrec
460dcc0a9e gen/init: Simplify Electrical Settings collection (and make them optional with litedram_gen).
When not specified in litedram_gen, the default settings will be used.
2021-10-07 13:44:25 +02:00
enjoy-digital
e1512553f8
Merge pull request from antonblanchard/ecp5-fixes
Fix a few issues with ECP5 standalone generator
2021-10-07 08:43:12 +02:00
Florent Kermarrec
ef8db14967 frontend/fifo: Fix data_width_ratio == 1 case. 2021-10-06 19:07:44 +02:00
Florent Kermarrec
136be83749 frontend/fifo: Revisit DRAM state to avoid deadlock situations when port_data_width != port_address_width. 2021-10-06 18:05:48 +02:00
Florent Kermarrec
1598b2733a frontend/fifo: Expose base/depth in bytes instead of DRAM's words. 2021-10-06 14:47:34 +02:00
Florent Kermarrec
f3d01ce98c litedram_gen: Expose ControllerSettings to user (and make cmd_buffer_length optional). 2021-10-06 14:31:57 +02:00
Anton Blanchard
99f53fcd1f phy/ecp5ddrphy: set cmd_delay from YAML config 2021-10-03 20:03:11 +11:00
Anton Blanchard
e0cf7d579e phy/ecp5ddrphy: set rtt_nom/rtt_wr/ron from YAML config 2021-10-03 20:02:51 +11:00
Florent Kermarrec
ce72e5b3fe modules: Add MT40A2G8/MT40A2G16. 2021-10-02 14:51:46 +02:00
Florent Kermarrec
feee435a57 ci: Install Meson/Ninja. 2021-10-01 14:48:09 +02:00
Florent Kermarrec
d2b2ba6d4b modules/IS43TR16512B: Review timings, add 800/1066/1333 speedgrades. 2021-09-30 17:56:40 +02:00
Florent Kermarrec
4adfff2c8b modules: Add IS43TR16512B. 2021-09-30 15:44:14 +02:00
Florent Kermarrec
3afd617455 frontend/fifo: Simplify level on _LiteDRAMFIFOCtrl, fix ctrl.write on _LiteDRAMFIFOWriter. 2021-09-24 19:34:55 +02:00
Florent Kermarrec
9e9c83ce40 litedram_gen: Add Auto-Flush to UART in FIFO mode.
In FIFO mode, backpressure is propagated to the UART and would stall the CPU
when the UART is not accepting data. Enable Auto-Flush on the UART to allow
DRAM initialization when the UART is not ready.
2021-09-24 13:37:19 +02:00
Florent Kermarrec
e52ece0b8a litedram_gen: Block accesses on User ports until the controller is successfully initialized.
This is convenient on some systems to decouple DRAM accesses from the init status reported by
the cores. User ports can still try to write/read data to the ports, the controlled will
just block the transfers and release them when it will be initialized.
2021-09-24 10:42:51 +02:00
Florent Kermarrec
b24381ca4a frontend/fifo: Simplify code and expose pre/post fifo_depth instead of writer/reader_fifo_depth. 2021-09-24 09:52:24 +02:00
Florent Kermarrec
3d3bf623aa frontend/fifo: Simplify, fix corner cases. 2021-09-23 23:22:51 +02:00
Florent Kermarrec
dd24073633 test/test_fifo: Use 4 x DRAM data-width in Bypass mode to use Pre/Post-Converter. 2021-09-23 18:57:00 +02:00
Florent Kermarrec
d9ec9882af frontend_fifo: Fix dram_data_cnt signal size. 2021-09-23 18:56:09 +02:00
Florent Kermarrec
49cf76af84 litedram_gen: Fix/Cleanup and . 2021-09-23 10:48:39 +02:00
enjoy-digital
6cfbaf80aa
Merge pull request from ozbenh/fix-no-cpu-gen
Fix generation with no CPU
2021-09-23 10:42:20 +02:00
enjoy-digital
f25247dd79
Merge pull request from jfng/fix_gen_uart
litedram_gen: Fix duplicate with_uart value when cpu_type is None.
2021-09-23 10:42:01 +02:00
enjoy-digital
27e632f0d4
Merge pull request from antmicro/acom/rdimm
modules: add more RDIMM modules
2021-09-23 10:41:21 +02:00
Alessandro Comodi
f3cf9ba116 phy: s7: add DDR4 memtype as well
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-09-22 17:01:37 +02:00
Benjamin Herrenschmidt
4fdb9a2cf2 Fix generation with no CPU
The various UART bits in there need to be skipped

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2021-09-22 21:01:56 +10:00
Florent Kermarrec
053434b9df litedram/gen/FIFO: Enable Bypass mode and do data-width adaptation directly in LiteDRAMFIFO. 2021-09-21 19:36:53 +02:00
Florent Kermarrec
2d4a47f260 frontend/fifo: Add initial optional/automatic Bypass implementation to LiteDRAMFIFO.
Bypass will provide lower latency and configurable data-width.
2021-09-21 19:23:36 +02:00
Jean-François Nguyen
9d8a0577e9 litedram_gen: Fix duplicate with_uart value when cpu_type is None. 2021-09-21 15:39:19 +02:00
Florent Kermarrec
43856dadd6 litedram_gen: Fix UART interrupt/polling. 2021-09-16 17:41:40 +02:00
Florent Kermarrec
e0e204a514 litedram_gen: Add FIFO Mode to UART (and rename serial IOs to uart).
It's more interesting in some design to access the UART through a FIFO like
interface than through RS232.
2021-09-16 17:01:00 +02:00
Alessandro Comodi
1b8e1f0b88 modules: add more RDIMM modules
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-09-16 14:28:19 +02:00
Florent Kermarrec
e9a4a746e9 CONTRIBUTORS: Update. 2021-09-15 14:43:09 +02:00
Florent Kermarrec
916f54e4f3 phy/s7ddrphy: Only add +1 to CL for DDR3 (thanks gsomlo). 2021-09-15 08:43:31 +02:00
Florent Kermarrec
6f323f6a7a phy/s7ddrphy: Add +1 to CL in MR register to increase sys_clk_freq range.
Allow successful DDR3 calibration at lower sys_clk_freq (tested down to 50MHz).
2021-09-14 16:33:33 +02:00
enjoy-digital
6a82042fee
Merge pull request from teknoman117/alchitry-ram-modules
Add AS4C128M16 DDR3L-1600 ram
2021-09-09 11:53:42 +02:00
Nathaniel R. Lewis
cbb699ce52 modules: add AS4C128M16 DDR3L module 2021-09-08 22:15:56 -07:00
Florent Kermarrec
db879ae3f7 litedram_gen: Fix missing user_port request for FIFO ports. 2021-09-03 10:31:08 +02:00
enjoy-digital
80398a8a15
Merge pull request from antmicro/jboc/dfi-converter-new
DFI rate converter - 2nd attempt
2021-08-23 19:34:10 +02:00