26cbb700bc
phy/lpddr5/sim: update delay for read data, add basic CAS handler
2021-10-26 12:22:30 +02:00
4e974738d1
phy/lpddr5: fix column address encoding/decoding
2021-10-26 12:22:30 +02:00
a015b66e4f
phy/lpddr5: fix write latency
2021-10-26 12:22:30 +02:00
e906c82ea2
phy/lpddr5/sim: debug serialization in gtkwave savefile
2021-10-26 12:22:30 +02:00
bfb8aaf44c
phy/lpddr5/sim: clean up write burst handling and implement read bursts
2021-10-26 12:22:30 +02:00
b8616fdfac
phy/lpddr5/sim: make adding module loggers simpler
2021-10-26 12:22:30 +02:00
5544875e1d
phy/lpddr5/sim: fix SimLogger timestamps
...
Timestamps were completely wrong for WCK as it is disabled
until the first write command and has varying frequency.
Now we use another clock which is always on to calculate time.
2021-10-26 12:22:30 +02:00
592ed9cac4
phy/lpddr5/sim: add initial data commands handling
2021-10-26 12:22:30 +02:00
6366a02389
phy/sim_utils: fix log level NONE not working
2021-10-26 12:22:30 +02:00
914d018cf8
phy/sim_utils: support low wait times (0/1) in PulseTiming
2021-10-26 12:22:30 +02:00
f9a11ea5ce
phy/lpddr5: start implementing DRAM simulator
2021-10-26 12:22:30 +02:00
2671508a11
phy/lpddr5: add simulation SoC
2021-10-26 12:22:30 +02:00
261f3dcd63
phy/lpddr5: add simulation phy
2021-10-26 12:22:30 +02:00
7cdf0e11ca
phy/lpddr5: add unit tests
2021-10-26 12:22:30 +02:00
68a0ac7e88
phy/lpddr5: add command adaptaion and base phy implementation
2021-10-26 12:22:30 +02:00
2b0f806c96
ci: Increase similarities with LiteX CI.
2021-10-26 12:15:39 +02:00
f537b5dd52
phy/s7ddrphy: Fix DDR2 case.
2021-10-18 15:33:56 +02:00
3202bc6acd
Merge pull request #277 from antmicro/acom/s7phy_ddr4
...
phy: s7: add DDR4 memtype as well
2021-10-18 13:35:15 +02:00
1d5192f572
litedram_gen/fifo: Avoid unnecessary get_port().
2021-10-08 08:52:50 +02:00
e1defa2687
litedram_gen: Fix rate for 7-Series.
2021-10-07 16:22:40 +02:00
1c59e77302
litedram_gen/add_sdram: Remove origin: no longer required.
2021-10-07 16:20:23 +02:00
f0a2f40a86
litedram_gen: Compute rate based on type of PHY (DDR3 rate is 1:2 with ECP5DDRPHY).
2021-10-07 15:41:51 +02:00
0bb3bff8af
litedram_gen: Set default csr_data_width to 32 (similar to LiteX).
2021-10-07 15:28:36 +02:00
6b0a35b309
litedram_gen: Add rst signal to CRG and use it as PLL reset.
2021-10-07 14:00:53 +02:00
ba0012f881
examples/versa_ecp5: Fix memtype.
2021-10-07 13:44:36 +02:00
460dcc0a9e
gen/init: Simplify Electrical Settings collection (and make them optional with litedram_gen).
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When not specified in litedram_gen, the default settings will be used.
2021-10-07 13:44:25 +02:00
e1512553f8
Merge pull request #280 from antonblanchard/ecp5-fixes
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Fix a few issues with ECP5 standalone generator
2021-10-07 08:43:12 +02:00
ef8db14967
frontend/fifo: Fix data_width_ratio == 1 case.
2021-10-06 19:07:44 +02:00
136be83749
frontend/fifo: Revisit DRAM state to avoid deadlock situations when port_data_width != port_address_width.
2021-10-06 18:05:48 +02:00
1598b2733a
frontend/fifo: Expose base/depth in bytes instead of DRAM's words.
2021-10-06 14:47:34 +02:00
f3d01ce98c
litedram_gen: Expose ControllerSettings to user (and make cmd_buffer_length optional).
2021-10-06 14:31:57 +02:00
99f53fcd1f
phy/ecp5ddrphy: set cmd_delay from YAML config
2021-10-03 20:03:11 +11:00
e0cf7d579e
phy/ecp5ddrphy: set rtt_nom/rtt_wr/ron from YAML config
2021-10-03 20:02:51 +11:00
ce72e5b3fe
modules: Add MT40A2G8/MT40A2G16.
2021-10-02 14:51:46 +02:00
feee435a57
ci: Install Meson/Ninja.
2021-10-01 14:48:09 +02:00
d2b2ba6d4b
modules/IS43TR16512B: Review timings, add 800/1066/1333 speedgrades.
2021-09-30 17:56:40 +02:00
4adfff2c8b
modules: Add IS43TR16512B.
2021-09-30 15:44:14 +02:00
3afd617455
frontend/fifo: Simplify level on _LiteDRAMFIFOCtrl, fix ctrl.write on _LiteDRAMFIFOWriter.
2021-09-24 19:34:55 +02:00
9e9c83ce40
litedram_gen: Add Auto-Flush to UART in FIFO mode.
...
In FIFO mode, backpressure is propagated to the UART and would stall the CPU
when the UART is not accepting data. Enable Auto-Flush on the UART to allow
DRAM initialization when the UART is not ready.
2021-09-24 13:37:19 +02:00
e52ece0b8a
litedram_gen: Block accesses on User ports until the controller is successfully initialized.
...
This is convenient on some systems to decouple DRAM accesses from the init status reported by
the cores. User ports can still try to write/read data to the ports, the controlled will
just block the transfers and release them when it will be initialized.
2021-09-24 10:42:51 +02:00
b24381ca4a
frontend/fifo: Simplify code and expose pre/post fifo_depth instead of writer/reader_fifo_depth.
2021-09-24 09:52:24 +02:00
3d3bf623aa
frontend/fifo: Simplify, fix corner cases.
2021-09-23 23:22:51 +02:00
dd24073633
test/test_fifo: Use 4 x DRAM data-width in Bypass mode to use Pre/Post-Converter.
2021-09-23 18:57:00 +02:00
d9ec9882af
frontend_fifo: Fix dram_data_cnt signal size.
2021-09-23 18:56:09 +02:00
49cf76af84
litedram_gen: Fix/Cleanup #276 and #278 .
2021-09-23 10:48:39 +02:00
6cfbaf80aa
Merge pull request #278 from ozbenh/fix-no-cpu-gen
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Fix generation with no CPU
2021-09-23 10:42:20 +02:00
f25247dd79
Merge pull request #276 from jfng/fix_gen_uart
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litedram_gen: Fix duplicate with_uart value when cpu_type is None.
2021-09-23 10:42:01 +02:00
27e632f0d4
Merge pull request #275 from antmicro/acom/rdimm
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modules: add more RDIMM modules
2021-09-23 10:41:21 +02:00
f3cf9ba116
phy: s7: add DDR4 memtype as well
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-09-22 17:01:37 +02:00
4fdb9a2cf2
Fix generation with no CPU
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The various UART bits in there need to be skipped
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2021-09-22 21:01:56 +10:00
Jędrzej Boczar
Florent Kermarrec
Anton Blanchard
Alessandro Comodi
Benjamin Herrenschmidt