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1541 Commits

Author SHA1 Message Date
Florent Kermarrec 053434b9df litedram/gen/FIFO: Enable Bypass mode and do data-width adaptation directly in LiteDRAMFIFO. 2021-09-21 19:36:53 +02:00
Florent Kermarrec 2d4a47f260 frontend/fifo: Add initial optional/automatic Bypass implementation to LiteDRAMFIFO. 
Bypass will provide lower latency and configurable data-width.
 2021-09-21 19:23:36 +02:00
Jean-François Nguyen 9d8a0577e9 litedram_gen: Fix duplicate with_uart value when cpu_type is None. 2021-09-21 15:39:19 +02:00
Florent Kermarrec 43856dadd6 litedram_gen: Fix UART interrupt/polling. 2021-09-16 17:41:40 +02:00
Florent Kermarrec e0e204a514 litedram_gen: Add FIFO Mode to UART (and rename serial IOs to uart). 
It's more interesting in some design to access the UART through a FIFO like
interface than through RS232.
 2021-09-16 17:01:00 +02:00
Alessandro Comodi 1b8e1f0b88 modules: add more RDIMM modules 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-09-16 14:28:19 +02:00
Florent Kermarrec e9a4a746e9 CONTRIBUTORS: Update. 2021-09-15 14:43:09 +02:00
Florent Kermarrec 916f54e4f3 phy/s7ddrphy: Only add +1 to CL for DDR3 (thanks gsomlo). 2021-09-15 08:43:31 +02:00
Florent Kermarrec 6f323f6a7a phy/s7ddrphy: Add +1 to CL in MR register to increase sys_clk_freq range. 
Allow successful DDR3 calibration at lower sys_clk_freq (tested down to 50MHz).
 2021-09-14 16:33:33 +02:00
enjoy-digital 6a82042fee
Merge pull request #274 from teknoman117/alchitry-ram-modules 
Add AS4C128M16 DDR3L-1600 ram
 2021-09-09 11:53:42 +02:00
Nathaniel R. Lewis cbb699ce52 modules: add AS4C128M16 DDR3L module 2021-09-08 22:15:56 -07:00
Florent Kermarrec db879ae3f7 litedram_gen: Fix missing user_port request for FIFO ports. 2021-09-03 10:31:08 +02:00
Jędrzej Boczar d95212bf0b test: check converters at higher data width ratios 2021-09-01 14:59:05 +02:00
Jędrzej Boczar 220538b56f phy: add implementation for Etron RPC DRAM 2021-09-01 14:59:01 +02:00
enjoy-digital 80398a8a15
Merge pull request #269 from antmicro/jboc/dfi-converter-new 
DFI rate converter - 2nd attempt
 2021-08-23 19:34:10 +02:00
enjoy-digital ca609005bc
Merge pull request #268 from antmicro/jboc/init-refactor 
Refactor init code generation
 2021-08-23 18:51:51 +02:00
Jędrzej Boczar 86cde91987 phy: fix typo (read_level -> read_leveling) 2021-08-12 12:14:51 +02:00
enjoy-digital 203cc73ceb
Merge pull request #271 from antonblanchard/fix-sim 
litedram_gen: Fix error with --sim option
 2021-08-09 19:46:17 +02:00
Anton Blanchard fe1bb083ef litedram_gen: Fix error with --sim option 
It looks like commit 317072a198 ("litedram_gen: Add initial SDRAM
support (with ULX3S example)") broke building with the --sim option.
 2021-08-09 10:38:54 +10:00
enjoy-digital ae139096c0
Merge pull request #267 from antmicro/jboc/lpddr4-update 
LPDDR4 minor refactor
 2021-08-06 14:39:42 +02:00
Jędrzej Boczar f4be065c09 phy/s7ddrphy: add compatibility with DFIRateConverter 2021-08-04 12:30:56 +02:00
Jędrzej Boczar 46ea844702 phy: update PHYs to set capabilities, delays/bitslips in PhySettings 2021-08-04 12:30:56 +02:00
Jędrzej Boczar 1d880c4db9 phy/dfi: add automatic PHY wrapper generation for DFIRateConverter 2021-08-04 12:30:56 +02:00
Jędrzej Boczar 43036c9576 test: update *_init.h reference 2021-08-04 12:30:56 +02:00
Jędrzej Boczar 89af25a697 phy/utils: DFI rate converter for creating PHY wrappers at slower clocks 2021-08-04 12:30:56 +02:00
Jędrzej Boczar 377746bfd8 init: add helper class to make C code generation simpler 2021-08-04 12:30:56 +02:00
Jędrzej Boczar 2200bd43a5 test/reference: update headers to include SDRAM_PHY_DFI_DATABITS 2021-08-04 12:30:56 +02:00
Jędrzej Boczar 993ba31697 init: generate `#define SDRAM_PHY_DFI_DATABITS` constant 2021-08-04 12:30:56 +02:00
Jędrzej Boczar 91cae335e5 init: add parentheses around #define with an expression 2021-08-04 12:30:56 +02:00
Jędrzej Boczar d20e8c763b phy: move simulation related utilities to sim_utils.py 2021-08-04 10:20:45 +02:00
Jędrzej Boczar 1bd9455216 phy/lpddr4: update docstring 2021-08-04 10:20:45 +02:00
Florent Kermarrec 4326fe7f36 bench/kcu105/xcu1525: Also use PHYPadsReducer to easily test various DFI sizes. 2021-07-13 14:57:42 +02:00
Florent Kermarrec fd8d6f8334 phy/mode: Switch litedram.common imports to * to also import get_default_cl_cwl/get_sys_latency. 2021-07-09 18:52:34 +02:00
Florent Kermarrec 5a4ed3d204 bench/arty/kc705: Use PHYPadsReducer to easily test various DFI sizes. 2021-07-09 17:58:40 +02:00
Florent Kermarrec 894c7fb49e phy/model: Let the model pick default settings when settings is set to None (In this case, data_width needs to be provided). 2021-07-08 09:09:05 +02:00
Florent Kermarrec daf2cb7d39 phy/model: Integrate sdram_module_nphases/get_sdram_phy_settings from litex_sim. 2021-07-08 09:02:13 +02:00
Florent Kermarrec a3aa4907f1 phy/lpddr4/simsoc: Change cpu_variant to lite and revert commented test_lpddr4_sim_x2rate_no_cache. 
(see #255).
 2021-07-02 09:24:11 +02:00
Florent Kermarrec a11d1b870d litedram_gen: Remove device limitation on GENSDRPHY/ECP5DDRPHY. 
By specifying FPGA device in .yml files for configs requiring  it.
 2021-07-02 09:15:42 +02:00
Florent Kermarrec 317072a198 litedram_gen: Add initial SDRAM support (with ULX3S example). 2021-07-02 09:01:31 +02:00
enjoy-digital 83d18f48c7
Merge pull request #257 from antmicro/jboc/lpddr5-split 
LPDDR4 code refactor
 2021-06-29 13:04:48 +02:00
Florent Kermarrec afd00f7873 bench/common/bench_test: Improve UART dump speed. 2021-06-29 12:38:44 +02:00
Florent Kermarrec e90aa5a4d5 bench/targets: Minor CRG cleanups. 2021-06-29 12:36:02 +02:00
Jędrzej Boczar 405cf8a8a5 phy/utils: add HoldValid stream primitive 2021-06-22 11:41:44 +02:00
Jędrzej Boczar 34fbe01a78 test/phy_common: make chunk size in PadsHistory summary configurable 2021-06-22 11:41:44 +02:00
Jędrzej Boczar eb6e7a1514 test/lpddr4: move dfi_data_to_dq to common code 2021-06-22 11:41:44 +02:00
Jędrzej Boczar fcda73a175 test/phy_common: simplify calls to run_simulation 2021-06-22 11:41:44 +02:00
Jędrzej Boczar 13cdbc0ed9 phy/utils: ConstBitSlip: allow for different bitrate relation of CA vs CS 2021-06-22 11:41:44 +02:00
Jędrzej Boczar da769094fd phy/lpddr4: fix edge case error with CommandsPipeline ignoring a command 
Command was being ignored when it occurred on the last phase and
the next command would invalidate the first phase. Now it is fixed
and a regression test is included. A fix in ConstBitSlip has been added
due to wrong Verilog being generated with cycles=1, register=False.
 2021-06-22 11:40:51 +02:00
Jędrzej Boczar baf9c07858 phy/utils: improve ConstBitSlip: 
* optional register=False to decrease latency by 1 cycle
* require explicit `cycles` as it influences latency (min_cycles
  still can be used)
* add unit tests
 2021-06-21 14:43:49 +02:00
Jędrzej Boczar 4a96be86c0 test/lpddr4: move run_simulation wrapper to phy_common.py 2021-06-21 14:43:49 +02:00