Florent Kermarrec
|
bc6a3f220a
|
examples/sim/sim/py: remove apb interface
|
2018-11-17 09:30:58 +01:00 |
|
Florent Kermarrec
|
e7e4bc527f
|
examples/sim: add ddr3 micron model
|
2018-11-17 09:20:34 +01:00 |
|
Florent Kermarrec
|
f219693635
|
examples: add simulation
|
2018-11-17 09:19:52 +01:00 |
|
Florent Kermarrec
|
f11506accd
|
examples/litedram_gen: cleanup pins definition
|
2018-10-15 09:38:34 +02:00 |
|
Florent Kermarrec
|
0f46dc4ab7
|
modules: add DDR3-800 timings for MT41J128M16 and use it on arty example
|
2018-10-01 11:59:54 +02:00 |
|
Florent Kermarrec
|
426ae23d2a
|
examples/litedram_gen: add sdram_module_speedgrade parameter
|
2018-10-01 11:48:15 +02:00 |
|
Florent Kermarrec
|
30c32f557c
|
example/litedram_gen: simplify clocking with new S7PLL module, a lot easier :)
|
2018-09-25 10:40:24 +02:00 |
|
Florent Kermarrec
|
37f1decfb2
|
multirank: one cs_n/cke/odt/clk per rank
|
2018-09-09 14:32:15 +02:00 |
|
Florent Kermarrec
|
8ddc6c735d
|
drive odt of all ranks, fixes and test non regression with 1 rank
|
2018-09-09 01:52:24 +02:00 |
|
Florent Kermarrec
|
cc481be81f
|
examples: add sdram_rank_nb and user_ports_id_width
|
2018-09-07 17:55:46 +02:00 |
|
Florent Kermarrec
|
1652ab95c8
|
examples/litedram_gen: fix address width of axi ports (addressing in bytes not words)
|
2018-09-05 09:13:47 +02:00 |
|
Florent Kermarrec
|
1e64b7f492
|
examples/litedram_gen: expose resp signals to user
|
2018-09-05 08:51:27 +02:00 |
|
Florent Kermarrec
|
de69867995
|
examples/litedram_gen: expose last signals to user
|
2018-09-05 08:32:49 +02:00 |
|
Florent Kermarrec
|
e8bd782999
|
examples/litedram_gen: expose burst signals to user
|
2018-09-05 08:31:57 +02:00 |
|
Florent Kermarrec
|
5e4dca9a7b
|
add examples with standalone cores for arty and genesys2
|
2018-08-31 23:20:47 +02:00 |