Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
296 Commits 5 Branches 14 Tags 5.7 MiB
Commit Graph

52 Commits

Author SHA1 Message Date
Florent Kermarrec f6797a16bb test/test_axi: add burst wrap test and fix code 2018-08-29 18:47:40 +02:00
Florent Kermarrec c15c47497a test/test_axi: split reads/writes generators 2018-08-28 14:09:12 +02:00
Florent Kermarrec 95cb7cdba5 test: rename read/write generators to handlers 2018-08-28 13:40:50 +02:00
Florent Kermarrec 10229d1e7d test/test_axi: improve test_axi2native 2018-08-28 13:39:11 +02:00
Florent Kermarrec 6a46ea3052 test/test_bist: add generator test, remove async test 2018-08-28 11:50:11 +02:00
Florent Kermarrec 7a5ac75e22 test/test_axi: improve test_axi2native 2018-08-27 18:39:36 +02:00
Florent Kermarrec c846b8b1c7 frontend/axi: add burst support (fixed/incr) 2018-08-27 16:21:12 +02:00
Florent Kermarrec 57157345cf frontend: add initial AXI support 2018-08-21 13:39:46 +02:00
Florent Kermarrec 2b20c11e2d add LiteDRAMNativePort to prepare for AXI, change some internals and API of get_port but keep retro-compatibility 
- LiteDRAMPort -> LiteDRAMNativePort
- aw -> address_width
- dw -> data_width
- cd -> clock_domain
 2018-08-21 13:21:04 +02:00
Florent Kermarrec c28a754867 test: update 2018-08-09 10:54:42 +02:00
Florent Kermarrec 697f46a97f replace litex.gen imports with migen imports 2018-02-23 13:39:23 +01:00
Felix Held 72b1b109b7 Fix all remaining indentation issues in python code 
I ran a script that shouldn't have missed any tab in the python source files.
 2018-01-13 13:22:08 +11:00
Florent Kermarrec 25d5674f33 test: remove test_bitslip (now in litex) 2017-04-24 18:49:20 +02:00
Florent Kermarrec 98d9f1ffc0 test/test_bitslip: simplify BitSlipModel 2017-02-10 13:18:11 +01:00
Florent Kermarrec 062177502b phy: add bitslip module (we need to implement it in logic for Kintex Ultrascale since not provided by ISERDESE3) 2017-02-10 08:59:13 +01:00
Florent Kermarrec 99550968e7 test: move BISTDriver to common and use it in test_bist_async 2017-01-17 15:18:10 +01:00
Florent Kermarrec d213a628f8 test/test_bist: use generator to corrupt memory (allow testing base address on checker/generator) 2017-01-17 14:35:34 +01:00
Florent Kermarrec 40168db0b4 test/test_bist: create BISTDriver to simplify test code 2017-01-17 14:31:24 +01:00
Florent Kermarrec c56f90e865 test/test_bist: simplify and test modules directly not through CSR 2017-01-17 14:14:50 +01:00
Florent Kermarrec ad304c8997 test: convert to python unittests and some cleanup 2017-01-17 13:18:11 +01:00
Tim 'mithro' Ansell c142db3966 Creating a utility module for easily scoping the LiteDRAMBISTChecker module. 2016-12-19 17:49:24 +01:00
Florent Kermarrec aac61f346e test: start fixing bist_tb 2016-12-17 19:24:12 +01:00
Tim 'mithro' Ansell e21b45b608 Merge remote-tracking branch 'upstream/master' into bist 2016-12-17 18:15:59 +01:00
Tim 'mithro' Ansell bc75d4f3d5 bist: Reworking as suggested by Florent. 2016-12-17 17:49:47 +01:00
Tim 'mithro' Ansell f1ad8991a4 bist: Working on improving the names of things. 2016-12-17 14:09:50 +01:00
Tim 'mithro' Ansell 8ff2f8779b bist: Adding "halt on error" functionality. 
Also include ability to see address of error and expected verse actual
data values.

Extend the test bench to test this functionality.
 2016-12-17 14:09:50 +01:00
Tim 'mithro' Ansell da144f41d4 bist: Refactoring test bench. 
Move a bunch of common code into common.py
 2016-12-17 14:09:50 +01:00
Tim 'mithro' Ansell dc14a98bf4 bist: s/shoot/start/ 2016-12-17 14:09:50 +01:00
Tim 'mithro' Ansell 086b905e59 bist: Improve the basic test bench a little. 2016-12-17 14:09:50 +01:00
Florent Kermarrec ad8ca86e13 frontend/adaptation: implement LiteDRAMReadPortUpConverter correctly 
still some corner cases to manage
 2016-06-15 23:57:16 +02:00
Florent Kermarrec 5823373243 frontend: introduce mode on ports: write, read or both 2016-06-15 17:51:46 +02:00
Florent Kermarrec e2b6bda7d0 test: add random and autocheck on downconverter_tb and upconverter_tb 2016-06-08 17:33:21 +02:00
Florent Kermarrec cb69561137 phy/model: add we_granularity parameter as simulator bug workaround (to be removed) 2016-05-28 13:02:40 +02:00
Florent Kermarrec 8ee2992e5b frontend/bist: simplify and use incrementing addressing 2016-05-26 12:04:41 +02:00
Florent Kermarrec 2445758eba +x on scripts 2016-05-26 11:10:03 +02:00
Florent Kermarrec b3a11fb669 frontend: move port adaptation modules to adaptation.py and do adaptation manually (and not in get_port) 2016-05-26 11:03:55 +02:00
Florent Kermarrec 3fe3a843e0 test: also test reads on downconverter/upconverter 2016-05-24 21:40:46 +02:00
Florent Kermarrec 32a6e25021 test: add upconverter_tb and some fixes 2016-05-24 21:14:49 +02:00
Florent Kermarrec de61cefb58 test: add downconverter_tb and some fixes 2016-05-24 20:48:26 +02:00
Florent Kermarrec 6f10314d43 frontend/bist: remove cd parameter (already available with dram_port.cd) 2016-05-23 17:37:30 +02:00
Florent Kermarrec b258c9a913 test: add bist_async_tb and some fixes 2016-05-23 17:20:42 +02:00
Florent Kermarrec cb324ea47c frontend/bist: LiteDRAMBISTGenerator can now be asynchronous 2016-05-23 14:17:22 +02:00
Florent Kermarrec f36c65b66f test: move DRAMMemory model to common 2016-05-23 13:30:38 +02:00
Florent Kermarrec 94d526a78c test/bist_tb: adapt to new interface 2016-05-23 13:27:29 +02:00
Florent Kermarrec 30bacfeb1b frontend: add LiteDRAMAsyncAdapter for asynchronous ports (need more tests) 2016-05-13 15:27:12 +02:00
Florent Kermarrec d7458a3c34 test: remove common 2016-05-04 01:16:29 +02:00
Florent Kermarrec a40b0f760c test/bist_tb: cleanup and add error check 2016-05-03 22:22:11 +02:00
Florent Kermarrec 836a9d4f00 test: removed bank_machine_tb (should be rewritten) 2016-05-03 19:25:39 +02:00
Florent Kermarrec 812d7dd7f0 frontend/bist: reword bist, add simulation, seems to work but need more testing 2016-05-03 19:24:33 +02:00
Florent Kermarrec 0ef987dab1 bankmachine: some changes and first tests 2015-09-27 23:42:05 +02:00