e446c06339
frontend/avalon: properly implement bursts ( #340 )
...
frontend/avalon: properly implement bursts
2023-05-31 08:14:52 +02:00
83a29b190d
Add support for clam shell topology ( #332 )
...
Add clam shell topology support.
2023-05-25 22:20:21 +02:00
d8c327b2b1
ci: Increase similarities with LiteX CI.
2023-05-23 16:41:59 +02:00
b452f09df6
frontend/avalon: Minor cosmetic fixes.
2023-05-23 14:57:36 +02:00
f1293eae1e
Avalon frontend for LiteDRAM ( #337 )
...
Add initial Avalon MM frontend + tests.
2023-05-23 14:52:05 +02:00
d7df59560e
setup.py: Prepare for 2023.04.
2023-05-07 20:47:47 +02:00
e452da7a00
Merge pull request #330 from timkpaine/tkp/ci
...
add manifest, uplift setup.py to pass twine checks
2023-04-11 17:01:51 +02:00
ad00237fa2
fix typo in ci
2023-04-07 19:08:35 -04:00
81203855a6
move up version
2023-04-07 19:06:45 -04:00
d7886c5fc5
add manifest, uplift setup.py to pass twine checks
2023-04-07 18:59:35 -04:00
6c8df7cc7b
Merge pull request #326 from trabucayre/gw2ddrphy_fix_warnings
...
phy/gw2ddrphy: supressing warnings about unconnected and bit length.
2023-02-08 19:12:01 +01:00
895b653a96
phy/gw2ddrphy: supressing warnings about unconnected and bit length.
2023-02-08 18:26:54 +01:00
455305a3ed
Merge pull request #322 from antmicro/msieron/make-tests-parallel-safe
...
Make tests safe to run in parallel
2023-01-31 08:25:18 +01:00
f94366c769
ci: Add help2man install for verilator compilation.
2023-01-20 19:14:17 +01:00
18f00151ed
ci: Specify verilator sha1 (Build broken with recent versions).
2023-01-19 10:01:38 +01:00
d95c1fc583
frontend/dma: Update omit signals in LiteDRAMDMAReader (Thanks @mohammadshahidzade).
2023-01-16 11:21:47 +01:00
a912a88081
Make tests safe to run in parallel
...
For example using pytest-parallel you can greatly reduce time it takes
to run all tests.
```
$ pytest --workers auto test
```
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2023-01-11 21:49:50 +01:00
b749e10970
Merge pull request #321 from antmicro/msieron/sdram-hw-test
...
frontend/bist: replicate LFSR output to fill the DRAM port
2023-01-11 19:10:23 +01:00
dad2c972f7
test/common: fix expected data for test_bist.py
...
Expected data needs to be replicated to fill given data_width.
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2023-01-11 17:13:52 +01:00
73c3ec6b68
frontend/bist: make LFSR output comb
...
Otherwise first output after reset is 0.
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2023-01-11 15:36:19 +01:00
f466c5f1db
frontend/bist: replicate LFSR output to fill DRAM port
...
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2023-01-11 15:36:19 +01:00
89581c1da7
gen: increase ROM size
...
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2023-01-11 15:36:19 +01:00
69b401dea1
test/test_init: Update.
2023-01-10 14:45:27 +01:00
d17b021aa2
Merge pull request #320 from antmicro/msieron/sdram-spd
...
init: Define `SDRAM_PHY_[DDR3|DDR4|...]` and `SDRAM_PHY_SUPPORTED_MEMORY`
2023-01-10 09:39:12 +01:00
8fa325310a
init: define SDRAM_PHY_SUPPORTED_MEMORY
...
To use as a default value when one can't read SDRAM size from the SPD.
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2023-01-09 16:03:09 +01:00
4c9f184566
init: define SDRAM_PHY_[DDR3|DDR4|...]
...
Will allow to ifdef code specific to some memory types like SPD reads.
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2023-01-09 16:03:09 +01:00
8339f54322
Merge pull request #319 from antmicro/msieron/fix-bist-errors
...
frontend/bist: properly signal finished writes
2023-01-05 22:21:23 +01:00
f45ca410ad
frontend/bist: properly signal finished writes
...
Without it, software was resetting the generator too early and wrong
data was being written to the RAM.
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2023-01-04 14:00:59 +01:00
3b2bcf91ed
ci: Switch to ubuntu 22.04 and increase similarities with LiteX's CI.
2022-12-09 11:06:58 +01:00
6b00d1adce
ci: Install RISC-V GCC with litex_setup.py.
2022-12-08 21:57:50 +01:00
379db85fc7
bench: Update with LiteX/LiteX-Boards changes.
2022-12-08 10:29:43 +01:00
1f1ab2d3ea
Merge pull request #314 from antmicro/msieron/fix-ddr4-sim
...
Fix DFITimingsChecker for DDR4 simulation
2022-11-18 12:47:13 +01:00
f25604c153
Fix DFITimingsChecker for DDR4 simulation
...
In case of DDR4 tRFC and tREFI timings are actually dictionaries with
timings specific for the chosen refresh mode.
Right now, it is impossible to simulate DDR4, because an exception
happens in `DFITimingsChecker.prepare_timings` method when indexing
`val` variable.
This is due to the fact, that in `DFITimingsChecker.__init__` we request
timing values from the module by name, ignoring the fact that some of
them (tRFC and tREFI) need to be first accessed using the chosen refresh
mode.
This commit fixes this error, by properly using `key` parameter when
calling `SDRAMModule.get` method to get only required timing.
If one were to fix it in `DFITimingsChecker.prepare_timings` method,
it would require duplicating logic from `SDRAMModule.get` so this is a
simpler and cleaner solution.
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2022-11-14 21:36:17 +01:00
c770dd62ed
test/test_lpddr5: Add tINIT2 as allowed warning.
2022-10-25 08:58:20 +02:00
d1529d7508
ci: Bump to ubuntu 20.04.
2022-10-14 18:17:02 +02:00
ae0763e252
axi: Update frontend/test with LiteX changes.
2022-09-15 17:52:01 +02:00
559dd24c99
phy/gw2ddrphy: Minor cosmetic cleanups.
2022-09-08 16:09:38 +02:00
cff8500f52
phy/gw2ddrphy: Add explicit TXCLK_POL and set it to 1 for DQS.
2022-09-08 16:03:39 +02:00
5b72d1a34a
gw2ddrphy: Add TCLK_SOURCE on DQS's OSER4_MEM.
2022-09-08 10:49:54 +02:00
ab9aec9129
phy/gw2ddrphy: Make oen signal names consistent.
2022-09-07 17:02:56 +02:00
22b823fdbc
phy/gw2ddrphy: Use same BitSlip moduel than ECP5DDRPHY.
2022-09-07 16:58:15 +02:00
f869d8e3d6
phy/gw2ddrphy: Increase similarities with ecp5ddrphy and add checkme notes.
2022-09-07 16:03:20 +02:00
434b00e65a
phy/gw2ddrphy: Fix Vendor name, update copyright.
2022-09-07 12:14:11 +02:00
c7eba6f704
Add intitial GW2DDRPHY (ported from ECP5DDRPHY), WIP.
2022-09-07 11:25:30 +02:00
dfc03a26b3
CONTRIBUTORS: Update.
2022-09-07 10:18:59 +02:00
3d066c87f9
ci: Add comment for Verilator build/install.
2022-06-27 17:46:37 +02:00
e662fadf8a
test/test_init: Update.
2022-05-10 10:38:55 +02:00
85e4c995d8
litedram/gen: .init renaming no longer required with https://github.com/enjoy-digital/litex/pull/1293 .
2022-05-09 18:02:57 +02:00
2b8af870c5
phy/usddrphy/Clk: Connect cdly_value only on first clk pad.
2022-05-02 17:34:52 +02:00
692355d120
CONTRIBUTORS: Update.
2022-05-02 13:43:38 +02:00
Hans Baier
Chen
Florent Kermarrec
Tim Paine
Gwenhael Goavec-Merou
Michal Sieron
Icenowy Zheng