Tim 'mithro' Ansell
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bc75d4f3d5
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bist: Reworking as suggested by Florent.
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2016-12-17 17:49:47 +01:00 |
|
Tim 'mithro' Ansell
|
f1ad8991a4
|
bist: Working on improving the names of things.
|
2016-12-17 14:09:50 +01:00 |
|
Tim 'mithro' Ansell
|
8ff2f8779b
|
bist: Adding "halt on error" functionality.
Also include ability to see address of error and expected verse actual
data values.
Extend the test bench to test this functionality.
|
2016-12-17 14:09:50 +01:00 |
|
Tim 'mithro' Ansell
|
da144f41d4
|
bist: Refactoring test bench.
Move a bunch of common code into common.py
|
2016-12-17 14:09:50 +01:00 |
|
Tim 'mithro' Ansell
|
dc14a98bf4
|
bist: s/shoot/start/
|
2016-12-17 14:09:50 +01:00 |
|
Tim 'mithro' Ansell
|
086b905e59
|
bist: Improve the basic test bench a little.
|
2016-12-17 14:09:50 +01:00 |
Florent Kermarrec
|
ad8ca86e13
|
frontend/adaptation: implement LiteDRAMReadPortUpConverter correctly
still some corner cases to manage
|
2016-06-15 23:57:16 +02:00 |
|
Florent Kermarrec
|
5823373243
|
frontend: introduce mode on ports: write, read or both
|
2016-06-15 17:51:46 +02:00 |
|
Florent Kermarrec
|
e2b6bda7d0
|
test: add random and autocheck on downconverter_tb and upconverter_tb
|
2016-06-08 17:33:21 +02:00 |
|
Florent Kermarrec
|
cb69561137
|
phy/model: add we_granularity parameter as simulator bug workaround (to be removed)
|
2016-05-28 13:02:40 +02:00 |
|
Florent Kermarrec
|
8ee2992e5b
|
frontend/bist: simplify and use incrementing addressing
|
2016-05-26 12:04:41 +02:00 |
|
Florent Kermarrec
|
2445758eba
|
+x on scripts
|
2016-05-26 11:10:03 +02:00 |
|
Florent Kermarrec
|
b3a11fb669
|
frontend: move port adaptation modules to adaptation.py and do adaptation manually (and not in get_port)
|
2016-05-26 11:03:55 +02:00 |
|
Florent Kermarrec
|
3fe3a843e0
|
test: also test reads on downconverter/upconverter
|
2016-05-24 21:40:46 +02:00 |
|
Florent Kermarrec
|
32a6e25021
|
test: add upconverter_tb and some fixes
|
2016-05-24 21:14:49 +02:00 |
|
Florent Kermarrec
|
de61cefb58
|
test: add downconverter_tb and some fixes
|
2016-05-24 20:48:26 +02:00 |
|
Florent Kermarrec
|
6f10314d43
|
frontend/bist: remove cd parameter (already available with dram_port.cd)
|
2016-05-23 17:37:30 +02:00 |
|
Florent Kermarrec
|
b258c9a913
|
test: add bist_async_tb and some fixes
|
2016-05-23 17:20:42 +02:00 |
|
Florent Kermarrec
|
cb324ea47c
|
frontend/bist: LiteDRAMBISTGenerator can now be asynchronous
|
2016-05-23 14:17:22 +02:00 |
|
Florent Kermarrec
|
f36c65b66f
|
test: move DRAMMemory model to common
|
2016-05-23 13:30:38 +02:00 |
|
Florent Kermarrec
|
94d526a78c
|
test/bist_tb: adapt to new interface
|
2016-05-23 13:27:29 +02:00 |
|
Florent Kermarrec
|
30bacfeb1b
|
frontend: add LiteDRAMAsyncAdapter for asynchronous ports (need more tests)
|
2016-05-13 15:27:12 +02:00 |
|
Florent Kermarrec
|
d7458a3c34
|
test: remove common
|
2016-05-04 01:16:29 +02:00 |
|
Florent Kermarrec
|
a40b0f760c
|
test/bist_tb: cleanup and add error check
|
2016-05-03 22:22:11 +02:00 |
|
Florent Kermarrec
|
836a9d4f00
|
test: removed bank_machine_tb (should be rewritten)
|
2016-05-03 19:25:39 +02:00 |
|
Florent Kermarrec
|
812d7dd7f0
|
frontend/bist: reword bist, add simulation, seems to work but need more testing
|
2016-05-03 19:24:33 +02:00 |
|
Florent Kermarrec
|
0ef987dab1
|
bankmachine: some changes and first tests
|
2015-09-27 23:42:05 +02:00 |
|
Florent Kermarrec
|
7732ff27a6
|
update code, start bankmachine refactoring and remove old code (will be rewritten)
|
2015-09-15 10:22:39 +02:00 |
|
Florent Kermarrec
|
230bad1b23
|
init structure
|
2015-02-22 18:25:36 +01:00 |