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litedram
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https://github.com/enjoy-digital/litedram.git
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bank_reordering
litedram
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examples
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Florent Kermarrec
0f46dc4ab7
modules: add DDR3-800 timings for MT41J128M16 and use it on arty example
2018-10-01 11:59:54 +02:00
..
arty_config.py
modules: add DDR3-800 timings for MT41J128M16 and use it on arty example
2018-10-01 11:59:54 +02:00
genesys2_config.py
examples/litedram_gen: add sdram_module_speedgrade parameter
2018-10-01 11:48:15 +02:00
litedram_gen.py
examples/litedram_gen: add sdram_module_speedgrade parameter
2018-10-01 11:48:15 +02:00