Jędrzej Boczar 12d66c119d phy/model: update DFITimingsChecker to new SDRAMModule timings format		2021-01-29 11:22:33 +01:00
..
core	phy/core: move rd/wrcmdphase and computation to Multiplexer.	2020-10-01 11:26:04 +02:00
frontend	frontend/bist: expose core for observation.	2020-10-19 09:47:33 +02:00
phy	phy/model: update DFITimingsChecker to new SDRAMModule timings format	2021-01-29 11:22:33 +01:00
__init__.py	update code, start bankmachine refactoring and remove old code (will be rewritten)	2015-09-15 10:22:39 +02:00
common.py	phy/gensdrphy: compute default cl from sys_clk_freq (similar what is already done on other PHYs).	2021-01-04 11:31:13 +01:00
dfii.py	add SPDX License identifier to header and specify file is part of LiteDRAM.	2020-08-23 15:52:08 +02:00
gen.py	litedram_gen: add initial Ultrascale+ support with XCU1525 .yml example.	2021-01-22 12:04:24 +01:00
init.py	ddr4: Enable Data Mask for DDR4 memory and invert its polarity.	2020-11-17 15:06:58 +01:00
modules.py	modules: extend parsing of timings to always allow (ck, ns) format	2021-01-29 11:16:16 +01:00