Jędrzej Boczar 12d66c119d phy/model: update DFITimingsChecker to new SDRAMModule timings format		2021-01-29 11:22:33 +01:00
..
__init__.py	phy/gensdrphy: add half-rate PHY	2020-07-13 17:03:01 +02:00
dfi.py	add SPDX License identifier to header and specify file is part of LiteDRAM.	2020-08-23 15:52:08 +02:00
ecp5ddrphy.py	phy/ecp5ddrphy: add clk_polarity parameter to allow inverting clk polarity (for boards with clk_p/n swapped).	2021-01-27 18:36:53 +01:00
gensdrphy.py	phy/gensdrphy: compute default cl from sys_clk_freq (similar what is already done on other PHYs).	2021-01-04 11:31:13 +01:00
model.py	phy/model: update DFITimingsChecker to new SDRAMModule timings format	2021-01-29 11:22:33 +01:00
s6ddrphy.py	phy/core: move rd/wrcmdphase and computation to Multiplexer.	2020-10-01 11:26:04 +02:00
s7ddrphy.py	phy/ecp5/s7/us: allow user to provide cl/cwl instead of default values.	2021-01-04 13:22:18 +01:00
usddrphy.py	phy/usddrphy: simplify tCK reference by using a specific ODELAYE3 in FIXED mode and keep the PHY in reset by default.	2021-01-21 18:18:39 +01:00