Florent Kermarrec f17037fdb2 bench/common: Cleanup, Increase sys_clk measure time to 5s.		2021-03-12 14:29:43 +01:00
..
arty.py	bench: Update with recent changes.	2021-03-12 10:25:11 +01:00
common.py	bench/common: Cleanup, Increase sys_clk measure time to 5s.	2021-03-12 14:29:43 +01:00
ddr3_mr_gen.py	bench: add DDR3 Mode Register settings generator.	2020-09-24 17:51:22 +02:00
ddr4_mr_gen.py	bench/ddr4_mr_gen.py: change default cl to 9 (cl value for sys_clk_freq=125e6).	2020-11-06 14:44:36 +01:00
genesys2.py	bench: Update with recent changes.	2021-03-12 10:25:11 +01:00
kc705.py	bench: Update with recent changes.	2021-03-12 10:25:11 +01:00
kcu105.py	bench: Update with recent changes.	2021-03-12 10:25:11 +01:00
xcu1525.py	bench/xcu1525: Update build directories.	2021-03-12 10:59:06 +01:00