Florent Kermarrec 9ce2f67bb1 frontend: add dram fifo (untested)		2017-06-23 22:00:49 +02:00
..
core	core: fix refresh (bug was reducing controller throughput by 2)	2016-06-13 13:11:41 +02:00
frontend	frontend: add dram fifo (untested)	2017-06-23 22:00:49 +02:00
phy	phy: BitSlip now integrated in LiteX	2017-04-19 09:58:27 +02:00
__init__.py	update code, start bankmachine refactoring and remove old code (will be rewritten)	2015-09-15 10:22:39 +02:00
common.py	frontend: add flush signal on dram ports and fix a specific case in LiteDRAMReadPortUpConverter	2016-12-15 19:07:43 +01:00
dfii.py	only use positive logic in the controller(cas/ras/we) and use Record/stream.Endpoint for command requests	2016-05-02 12:18:56 +02:00
modules.py	modules: add MT41J256M16	2017-03-14 20:59:02 +01:00