Florent Kermarrec
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95081445e7
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liteeth_gen/A7_1000BASEX: Add support for 156.25MHz refclk_freq and fix 200MHz to 125MHz.
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2024-01-19 21:40:45 +01:00 |
|
Florent Kermarrec
|
c05de191e2
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liteeth_gen: Add specific A7_1000BASEX support and example configuration.
Adapted from known working targets but untested on hardware.
|
2024-01-18 13:27:32 +01:00 |
rowanG077
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b8745ff99a
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gen.py: Add UDP raw mode
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2023-07-10 17:18:45 +02:00 |
|
Florent Kermarrec
|
f943a395f6
|
liteeth_gen: Add DHCP support and demonstrate it on udp_usp_gth_sgmii.yml config.
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2023-07-03 18:07:36 +02:00 |
|
Florent Kermarrec
|
65ef1930f5
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liteeth_gen: Add refclk_freq parameter for SGMII/1000BaseX.
|
2023-06-23 12:51:15 +02:00 |
|
Florent Kermarrec
|
0d59ea180f
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examples: Add udp usp gth sgmii example.
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2023-06-22 16:50:24 +02:00 |
Victor Suarez Rovere
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5f14bd4a7f
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add initial support to generate verilog code using wishbone or axi-lite bus standard (depending on the .yml file)
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2022-10-31 20:43:53 -03:00 |
|
Florent Kermarrec
|
b0e7243123
|
liteeth_gen: Add data_width support (For 32/8-bit datapath).
|
2022-05-16 13:38:05 +02:00 |
|
Florent Kermarrec
|
ba20fc7b71
|
liteeth_gen/udp: Improve flexibility and add support for multiple UDP virtual channels.
|
2022-01-28 10:11:45 +01:00 |
|
Florent Kermarrec
|
680806997d
|
liteeth_gen/udp: Directly integrate UDPStreamer to simplify use and just expose a LiteX-Stream/AXI-ST interface.
|
2022-01-26 11:18:48 +01:00 |
|
Florent Kermarrec
|
f264c9d5d5
|
liteeth_gen: Add toolchain support/parameter.
LiteX code specialization/generation can be different between toolchain (For the same vendor).
Add parameter to configure it from the .yml file.
|
2022-01-26 09:57:43 +01:00 |
|
Florent Kermarrec
|
53057121e7
|
examples: remove old examples and update README (new benches/examples will be added).
|
2020-11-23 12:54:09 +01:00 |
Konrad Beckmann
|
054eebc25f
|
test_etherbone: Fix import of etherbone module
|
2020-09-30 21:04:11 +02:00 |
|
Florent Kermarrec
|
64b85e621e
|
add SPDX License identifier to header and specify file is part or LiteEth.
Artix7/Ultrascale 1000BaseX is reused from MiSoC/LiteEthMini, specify it.
|
2020-08-23 16:07:12 +02:00 |
|
Florent Kermarrec
|
1d76d02ea6
|
frontend: rename tty to stream (tty was too specific since modules can be used for any kind of data stream).
|
2020-07-13 10:08:50 +02:00 |
|
Florent Kermarrec
|
8e1185711b
|
common: remove Port.connect and use 2 separate Record.connect.
|
2020-06-22 14:36:44 +02:00 |
|
Florent Kermarrec
|
92c30489ae
|
examples: use CRG from litex.build.
|
2020-04-10 10:31:14 +02:00 |
|
Florent Kermarrec
|
400ca97f45
|
examples: increase clk_freq to 125MHz on udp_s7phyrgmii.yml.
|
2020-03-19 22:01:33 +01:00 |
Xiretza
|
2e9121d330
|
Allow changing all SoC options through YAML config
|
2020-03-17 18:52:44 +01:00 |
|
Xiretza
|
7a44209f77
|
Make memory/CSR regions customizable in config
Also remove interrupt mapping, since it's unused without a CPU anyway.
|
2020-02-12 15:55:04 +01:00 |
|
Xiretza
|
ca9cbd1555
|
Move more options to config file
|
2020-02-12 15:55:04 +01:00 |
|
Florent Kermarrec
|
358bc23cd4
|
examples/.ymls: add separators
|
2020-02-12 11:23:33 +01:00 |
|
Florent Kermarrec
|
fcadd60cea
|
liteeth/gen: initial switch to YAML config file (similar to LiteDRAM/LitePCIe)
|
2020-02-12 00:18:22 +01:00 |
|
Florent Kermarrec
|
ddd0431373
|
examples: use integrated sram instead of external one. (Also fix regression with new SoC that no longer support address decoders passed to add_wb_slave)
|
2020-02-11 21:22:13 +01:00 |
|
Florent Kermarrec
|
bb01840b12
|
add initial LiteEth standalone core generator from examples/core.py
|
2019-11-24 11:22:51 +01:00 |
|
Florent Kermarrec
|
c1783ce554
|
examples/targets: update and cleanup
|
2019-11-23 19:49:23 +01:00 |
|
Florent Kermarrec
|
d3b2f3d361
|
examples/targets: udpate analyzer
|
2019-11-23 15:47:42 +01:00 |
|
Florent Kermarrec
|
dc8ddf6895
|
examples: keep up to date with LiteX
|
2019-11-23 15:23:24 +01:00 |
|
Florent Kermarrec
|
e980b603cc
|
example/udp_loopback: simplify/cleanup and make it more generic
|
2019-11-20 08:53:16 +01:00 |
Yehowshua Immanuel
|
50cc7d0671
|
examples: add practical UDP loopback example with Versa ECP5
|
2019-11-20 08:18:50 +01:00 |
|
Florent Kermarrec
|
4bc79cefd8
|
examples/targets/core: update
|
2019-09-24 12:53:06 +02:00 |
|
Florent Kermarrec
|
ad187d35f2
|
add CONTRIBUTORS file and add copyright header to all files
|
2019-06-24 11:43:10 +02:00 |
|
Florent Kermarrec
|
fd6d6c30ba
|
mac: update imports
|
2019-06-24 11:23:13 +02:00 |
|
Florent Kermarrec
|
40b99ecc05
|
test: use new RemoteClient import
|
2018-09-23 10:28:50 +02:00 |
|
Florent Kermarrec
|
94af3d63d9
|
README: update and rename example_designs to examples
|
2018-08-31 08:26:37 +02:00 |