880bdf43b0
liteeth/phy/rmii: Add 10Mbps/100MBps dynamic speed support.
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Speed still needs to be changed manually, we could try to add automatic detection in the future.
2024-09-26 12:57:29 +02:00
7f91ebbee5
Merge pull request #172 from VOGL-electronic/phy_rmii_fix_efinix_sdr
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phy/rmii: fix it for efinix
2024-09-26 11:55:32 +02:00
90b1a18485
Merge pull request #173 from trabucayre/efinix_rework_clkinput_pll
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phy/trionrgmii,titaniumrgmii: replaces str by ClockSignal for ClkInput and PLL
2024-09-26 11:51:44 +02:00
3696ef82bb
phy/trionrgmii,titaniumrgmii: replaces str by ClockSignal for ClkInput and PLL
2024-09-26 11:03:12 +02:00
3693c61cbe
phy/rmii: fix it for efinix
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On efinix platforms the clk signal of
`SDROutput` and `SDRInput` has to come
from the PLL.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-25 17:06:29 +02:00
2b0156e9b3
liteeth/mac/core: Allow PHY to enforce with_preamble_crc/with_padding parameters.
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Avoid exposing these parameters up to add_ethernet since appropriate behaviour is generally
directly related to the type of PHY (ex LiteEthPHYModel or custom/specialized PHY).
2024-09-23 16:35:28 +02:00
1d19de09ef
phy/rmii: Cosmetic cleanups.
2024-09-23 15:30:08 +02:00
f252eed154
phy/rmii/LiteEthPHYRMIIRX: Avoid FSM, simplify and add comments.
2024-09-23 15:23:38 +02:00
5438ff01e1
phy/rmii/LiteEthPHYRMIIRX: Avoid reset on converter and improve frame delimitation.
2024-09-23 12:22:57 +02:00
66b277a80b
phy/rmii: Also use SDROutput on TX and add comments/simplify.
2024-09-23 11:53:42 +02:00
3cfbf007ab
phy/rmii/LiteEthPHYRMIIRX: Use SDRInput on pads.csr_dv/rx_data to make it clear input is synchronous.
2024-09-23 11:42:30 +02:00
5538c87115
liteeth/phy/rmii: Move crs first/last detection outside of FSM.
2024-09-23 11:30:57 +02:00
1c89387d09
liteeth/phy/rmii: Replace MuliReg with stream.Delay.
2024-09-23 11:05:23 +02:00
af746ec973
liteeth/core/__init__.py: Switch to LiteXModule.
2024-09-20 16:19:03 +02:00
a75f4e5ea7
CONTRIBUTORS: Update.
2024-09-20 12:28:14 +02:00
28cf1c267b
LICENSE/README.md: Bump year.
2024-09-20 12:27:07 +02:00
dd1988a40d
frontend/etherbone/LiteEthEtherbonePacketRX: Only enable LiteEthLastHandler for 64-bit case.
2024-09-20 12:15:18 +02:00
d5a9f9d2d4
core: Expose icmp_fifo_depth paramter.
2024-09-19 22:18:53 +02:00
b61c3e5bd1
Merge pull request #171 from GustavsC/master
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Add support for Virtex7-1000Base
2024-09-18 11:19:01 +02:00
db1795171b
Merge branch 'enjoy-digital:master' into master
2024-09-17 16:56:26 -03:00
5bc0ec00be
Merge pull request #169 from VOGL-electronic/fix_phy_rmii_efinix
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phy: rmii: use ClockSignal(refclk_cd) to drive DDROutput
2024-09-17 21:20:30 +02:00
ac70566ab4
Create v7_1000basex.py
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Adding Virtex 7 1000 Basex
2024-09-17 11:24:38 -03:00
b573e1267c
phy/xgmii: Add Clk/Data Pads definition to avoid duplication in PHYs.
2024-09-16 11:35:33 +02:00
7e072a997b
phy: rmii: use ClockSignal(refclk_cd) to drive DDROutput
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use ClockSignal(refclk_cd) to drive DDROutput.
with this the DDROutput can be used on efinix platforms.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-13 12:05:38 +02:00
78513c2ba7
frontend/stream: Add 64-bit data_width support.
2024-09-12 18:46:11 +02:00
b1f916a447
frontend/etherbone: Add LiteEthLastHandler to LiteEthEtherbonePacketRX for 64-bit data-width support.
2024-09-12 13:33:49 +02:00
0b5389feab
mac: Move LiteEthMACLastBE module to common.py and rename to LiteEthLastHandler.
2024-09-12 13:32:38 +02:00
a2a862dc1b
liteeth_gen: Add XGMII PHY support (Transceiver still need to be integrated externally).
2024-09-11 15:21:24 +02:00
74bd085757
Merge pull request #168 from trabucayre/efinix_rework_primitives
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Efinix rework primitives
2024-09-10 18:41:06 +02:00
9496fd229f
phy/titaniumrgmii.py: uses ClockSignal for DDRInput/DDROutput/ClkOutput, added cd for eth_tx_delayed, removed name=xxx for clkout with a cd
2024-09-10 11:52:48 +02:00
88387cbd11
phy/trionrgmii.py: use ClockSignal for ClkOutput 'o', remove name parameter when a cd is used
2024-09-10 11:27:47 +02:00
577a47222c
phy/trionrgmii.py: DDRInput/DDROutput switch clk to a ClockSignal
2024-09-10 08:09:03 +02:00
ea07f5c421
phy/titaniumrgmii,trionrgmii: fixed pll clkin name by appending a '0' to match ClkInput / get_pin_name modifications introduces by LiteX commit d3161ad74c4b2afd5635f76f566c37f362eb166a
2024-09-04 14:48:34 +02:00
ecaebfe645
phy/trionrgmii.py: fixed RX and TX sides. RX: forces phase align by usign it as PLL's feedback. TX: reduces PLL phase shift 90 -> 45
2024-09-03 15:08:09 +02:00
9780327251
Merge pull request #167 from VOGL-electronic/fix_liteethmac
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mac/__init__.py: Fix LiteEthMAC.
2024-08-27 09:20:33 +02:00
7086f6d0ea
mac/__init__.py: Fix LiteEthMAC.
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This fixes LiteEthMAC and
LiteEthMACCoreCrossbar.
Its also renames the depacketizer in
LiteEthMACCoreCrossbar for mac filtering
to filter_depacketizer, so it is not mixed up
with self.depacketizer.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-08-27 08:41:26 +02:00
edc7188faa
mac/__init__.py: Improve/Cleanup LiteEthMAC.
2024-08-19 10:19:53 +02:00
bfc07e543a
mac/__init__: Add comments on RX broadcard/filtering and minor cleanups.
2024-08-19 09:58:53 +02:00
0bb6c53795
mac/__init__.py: Switch to LiteXModule and cosmetic improvements.
2024-08-19 09:38:35 +02:00
55bae6b7b4
Merge pull request #165 from VOGL-electronic/fix_packet_handling
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MAC: Implement address filtering for logic interface in hybrid mode
2024-08-19 09:27:54 +02:00
9531af62a7
Merge pull request #166 from VOGL-electronic/fix_etherbone
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Fix etherbone reads
2024-08-19 09:26:25 +02:00
964df3ac2f
phy/a7_gtp: Add separators and remove __all__.
2024-08-19 09:24:34 +02:00
c04ac8f698
Merge pull request #164 from VOGL-electronic/optional_liteiclink
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Only import liteiclink when required
2024-08-19 09:17:01 +02:00
d4fa6a2f4a
phy/a7_gtp: Add additionnal comment to #163 and express delay in us.
2024-08-19 09:16:20 +02:00
32df4523ba
Merge pull request #163 from cyntem/patch-1
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Update a7_gtp.py transceiver resets have to stay low for 10us.
2024-08-19 09:14:05 +02:00
7b4429e814
Fix etherbone reads
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Since https://github.com/enjoy-digital/litex/pull/1999 , etherbone reads
might result in garbage being output. This is caused by `be` not being
set during the read.
Fixes https://github.com/enjoy-digital/litex/issues/2031
Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
2024-08-18 17:20:05 +02:00
da6e053f78
mac: implement mac filtering for logic interface in hybrid mode
2024-07-22 12:57:44 +02:00
85c3ab2c51
Only import liteiclink when required
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As liteiclink is only used in the phy implementations of a few Xilinx/AMD
FPGAs, it does not make sense that it would be required to build liteeth
for any FPGA.
Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
2024-07-14 22:36:26 +02:00
4653a09aec
Update a7_gtp.py
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After testing several boards with XC7A200T chips, I found, that SFP works well only with setting more than 10us. The most of the XC7A200T chips works with 500ns, but some boards need 10us.
2024-07-14 20:05:00 +03:00
583137eaf3
phy/1000basex: Use pll.config["d"] to compute TX_PROGDIV_CFG/RX_PROGDIV_CFG to fix behavior with 200MHz ref_clk_freq.
2024-07-10 16:21:11 +02:00
Florent Kermarrec
Gwenhael Goavec-Merou
Fin Maaß
Gustav
GustavsC
Matthias Breithaupt
cyntem