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Author SHA1 Message Date
Sergey Razumov
9a904fb8dc Artix 7 2500BASE-X 2023-08-31 11:04:14 +03:00
Gwenhael Goavec-Merou
23035e7c63 phy/rmii: merging cd_eth_rx, cd_eth_tx and clock pads when refclk_cd is None 2023-08-30 19:46:26 +02:00
Florent Kermarrec
0f055b1c0f phy/efinix: IO exclusion on DDROutput/Input now directly done in LiteX. 2023-08-30 18:09:45 +02:00
Florent Kermarrec
8436d775f6 phy/efinix: Switch to new DDROutput/Input now supported in LiteX for Efinix. 2023-08-30 11:30:29 +02:00
Florent Kermarrec
b201aeb083 phy/efinix: Directly exclude IOs when primitive is used, avoid having to do it in user design. 2023-08-30 08:54:46 +02:00
Icenowy Zheng
ab93bc8ed1 phy: add initial GW5RGMII (RGMII for Gowin Arora V series) 
Tested on Sipeed Tang Mega 138K ES (GW5AT-138 ES).

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2023-08-15 11:10:28 +08:00
Florent Kermarrec
f0c876ca77 core/arp: Only increment clear_timer in IDLE state and change timeout to 1s. 2023-08-02 14:54:32 +02:00
Florent Kermarrec
cb1e1932b3 global: Use new WaitTimer integrated cast to int. 2023-08-01 14:42:16 +02:00
enjoy-digital
16224432d9
Merge pull request #142 from enjoy-digital/arp_table 
Simplify ARP and add proper multi-entry ARP Table.
 2023-07-31 18:03:25 +02:00
Florent Kermarrec
ea45c8704f core/arp: Add enable signals for Cache/Clear for optional external control. 2023-07-31 17:26:58 +02:00
Florent Kermarrec
c5b53326bb core/arp: Add clear timer to clear cache periodically and minor cleanups. 2023-07-31 16:57:42 +02:00
Florent Kermarrec
b74618d1ed core/arp: Switch LiteEthARPCache to a proper Memory and allow multiple entries. 2023-07-31 16:15:10 +02:00
Florent Kermarrec
dc7ed0de6f core/arp: Move ARP cache logic to LiteEthARPCache and define interfaces. 2023-07-31 14:46:16 +02:00
Florent Kermarrec
fba8925f60 core/arp: Another FSM simplification pass. 2023-07-31 14:15:28 +02:00
Florent Kermarrec
4327adcab4 core/arp: Simplify FSM CHECK_TABLE state. 2023-07-31 12:04:34 +02:00
Florent Kermarrec
f33d5b5959 core/arp: Add CHECK_REQUEST state to generate failed response if so and simplify FSM. 2023-07-31 11:45:13 +02:00
Florent Kermarrec
538a4e407c core/arp: Cosmetic cleanups. 2023-07-31 11:23:12 +02:00
Florent Kermarrec
fc4ed41dcf core/arp: Simplify request_pending. 2023-07-31 11:16:19 +02:00
Florent Kermarrec
4dbcb53411 core/arp: Simplify request_counter/timer. 2023-07-31 11:12:58 +02:00
Florent Kermarrec
0abd3fa9fc core/arp: Simplify request_ip_address. 2023-07-31 11:00:31 +02:00
Florent Kermarrec
df053ae739 phy/trionrgmii: Add missing with_reset. 2023-07-27 15:01:10 +02:00
Florent Kermarrec
39fe055c19 core/arp: Allow clk_freq to be passed as float. 2023-07-25 14:13:02 +02:00
enjoy-digital
32de4f041e
Merge pull request #137 from rowanG077/udpraw 
gen.py: Add UDP raw mode
 2023-07-21 15:05:24 +02:00
Florent Kermarrec
eb63b771a7 frontend/stream/LiteEthStream2UDPTX: Latch ip_address/udp_port in Idle state. 
Useful when ip_address/udp_port are dynamic signals.
 2023-07-18 16:38:13 +02:00
rowanG077
b8745ff99a gen.py: Add UDP raw mode 2023-07-10 17:18:45 +02:00
Florent Kermarrec
64cceb24b1 liteeth_gen: Expose reset. 2023-07-10 12:59:17 +02:00
Florent Kermarrec
7537dcb0fc phy/100basex: Rename crg_reset to reset. 2023-07-10 12:58:55 +02:00
Florent Kermarrec
0d89c59c89 core/icmp/LiteEthICMPEcho: Verify packet length before storing in buffer and drop if too long for configurated depth. 2023-07-10 11:13:52 +02:00
Florent Kermarrec
31893a2d25 core/icmp: Add fifo_depth parameter. 2023-07-10 10:58:34 +02:00
Florent Kermarrec
01bdf0de07 frontend/etherbone: Switch to LiteXModule. 2023-07-10 10:37:00 +02:00
Florent Kermarrec
e7ea355959 core/udp: Switch to LiteXModule. 2023-07-10 10:24:56 +02:00
Florent Kermarrec
f3d08e589b packet: Switch to LiteX/Module. 2023-07-10 10:24:37 +02:00
Florent Kermarrec
8a3534f84f core/ip: Switch to LiteXModule. 2023-07-10 10:10:51 +02:00
Florent Kermarrec
f74beeeb71 core/icmp: Switch to LiteXModule. 2023-07-10 09:59:37 +02:00
Florent Kermarrec
01073323ff core/arp: Switch to LiteXModule. 2023-07-10 09:57:54 +02:00
Florent Kermarrec
4bbb14a59c crossbar: Switch to LiteXModule. 2023-07-10 09:53:45 +02:00
Florent Kermarrec
1be13c2ece phy/pcs_1000basex: Switch to litex.gen.genlib.cdc. 2023-07-06 22:29:13 +02:00
Florent Kermarrec
e5168fe142 global: Switch to litex.gen.genlib.misc. 2023-07-06 22:06:37 +02:00
Florent Kermarrec
4954026a26 core/dhcp: Add Lumiguide to copyright. 2023-07-06 21:35:24 +02:00
Florent Kermarrec
5c806c150e core/LiteEthUDP/IPCore: Use buffered TX/RX CDC as default since improving timing on low-end FPGAs and not impacting much resources. 2023-07-06 19:24:12 +02:00
Florent Kermarrec
70a89eafaa core/dhcp: Add missing TX/RX reset on timeout. 2023-07-04 18:19:35 +02:00
Florent Kermarrec
d29d90cd78 liteeth_gen: Switch to LiteXModule and remove old TODO. 2023-07-03 19:15:12 +02:00
Florent Kermarrec
f8594ae429 phy/ecp5rgmii: Review/cleanup tx_clk addition. 2023-07-03 19:10:42 +02:00
Florent Kermarrec
8ae7649d03 liteeth: Review TX/RX CDC changes (cosmetic cleanups). 2023-07-03 19:04:58 +02:00
enjoy-digital
322d8625b5
Merge pull request #127 from rowanG077/master 
Add core CDC depth and buffered parameters.
 2023-07-03 18:57:24 +02:00
enjoy-digital
815c742c74
Merge branch 'master' into master 2023-07-03 18:55:44 +02:00
Florent Kermarrec
6bdc13bb07 README: Update. 2023-07-03 18:08:12 +02:00
Florent Kermarrec
f943a395f6 liteeth_gen: Add DHCP support and demonstrate it on udp_usp_gth_sgmii.yml config. 2023-07-03 18:07:36 +02:00
Florent Kermarrec
4afd325fc6 core/dhcp: Shorten offered_ip_address to ip_address. 2023-07-03 18:06:48 +02:00
Florent Kermarrec
7a988bee22 core: Add initial/minimal DHCP support to hardware stack. 
Ex of use in a  SoC that issues a DHCP request per second:

from liteeth.core.dhcp import LiteEthDHCP

from migen.genlib.misc import WaitTimer

# Signals.
ip_address  = Signal(32)
mac_address = Signal(48, reset=0x10e2d5000001)

# Request Timer.
self.dhcp_timer = dhcp_timer = WaitTimer(int(sys_clk_freq/2))
self.comb += self.dhcp_timer.wait.eq(~self.dhcp_timer.done)

# DHCP.
dhcp_port = self.ethcore_etherbone.udp.crossbar.get_port(68, dw=32, cd="sys")
self.dhcp = dhcp = LiteEthDHCP(udp_port=dhcp_port, sys_clk_freq=sys_clk_freq)
self.comb += [
    dhcp.start.eq(self.dhcp_timer.done),
    dhcp.mac_address.eq(mac_address),
]

self.sync += [
    If(dhcp.done,
        ip_address.eq(dhcp.offered_ip_address)
    )
]
 2023-07-03 17:44:48 +02:00