Florent Kermarrec
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c15f089eba
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bump to 0.2.dev
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2018-02-23 13:39:53 +01:00 |
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Florent Kermarrec
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c42aa09878
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uniformize litex cores
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2018-02-22 10:12:33 +01:00 |
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enjoy-digital
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4e08d6e9f9
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Merge pull request #13 from felixheld/crc_pythonize
pythonize CRC calculation
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2018-02-22 09:00:25 +01:00 |
Felix Held
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9dcc7bc65e
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mac/crc.py: make crc calculation more pythonic
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2018-02-21 23:20:03 +01:00 |
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Felix Held
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2ceaa74caf
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clarify the comments in mac/crc.py code
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2018-02-21 23:05:32 +01:00 |
Tim Ansell
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8fc7161036
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Merge pull request #11 from felixheld/indentation-fixes
Fix all remaining indentation issues in python code
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2018-01-13 13:36:32 +11:00 |
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Felix Held
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20af2bf201
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Fix all remaining indentation issues in python code
I ran a script that shouldn't have missed any tab in the python source files.
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2018-01-13 13:23:18 +11:00 |
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Florent Kermarrec
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2788294834
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core/mac/sram: add csr for fifo level of sram reader (for the linux driver)
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2017-12-31 07:12:55 +01:00 |
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Florent Kermarrec
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c9ec30df2f
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core/mac: apply changes from misoc: remove gap_checker in rx, add preamble errors, fix preamble checker
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2017-12-30 18:32:50 +01:00 |
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Florent Kermarrec
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ccdb85bcb7
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doc: add simple architecture diagram
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2017-11-13 17:39:09 +01:00 |
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Florent Kermarrec
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edb51944d5
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Merge branch 'master' of https://github.com/enjoy-digital/liteeth
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2017-11-06 19:02:42 +01:00 |
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Florent Kermarrec
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a20ff49c90
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example_designs/test: keep up to date with litescope
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2017-11-06 19:01:51 +01:00 |
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Florent Kermarrec
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26c01a1627
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core/mac/crc: fix crc_error generation
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2017-11-01 23:23:02 +01:00 |
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Florent Kermarrec
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eaf4acc3f5
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core/mac: apply misoc changes (72faa2c)
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2017-11-01 21:11:08 +01:00 |
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Florent Kermarrec
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937c240727
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test: fix test_model
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2017-09-25 13:12:30 +02:00 |
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enjoy-digital
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48fb4647bd
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Merge pull request #6 from enjoy-digital/port-1234
Adding TCP port 1234 to Etherbone dissector.
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2017-09-01 15:23:22 +02:00 |
Tim Ansell
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00e6ded2e9
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Adding TCP port 1234 to Etherbone dissector.
LiteEth designs seem to commonly use TCP port 1234.
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2017-09-01 23:16:09 +10:00 |
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Florent Kermarrec
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c43fb269a7
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frontend/etherbone: timing optimizations
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2017-07-19 12:20:17 +02:00 |
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Florent Kermarrec
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042d3aee3e
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frontend/etherbone: fix cd="sys case
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2017-07-15 22:10:48 +02:00 |
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Florent Kermarrec
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1127e3a615
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core/udp: simplify LiteEthUDPCrossbar.get_port when used with cdc
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2017-07-01 13:14:13 +02:00 |
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Florent Kermarrec
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b870d13d96
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global: reset_less optimizations
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2017-07-01 11:22:26 +02:00 |
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Florent Kermarrec
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34460cec47
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core/udp: add cdc support (untested)
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2017-06-30 11:01:44 +02:00 |
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Florent Kermarrec
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5bc6e879ae
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update litescope
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2017-06-23 09:14:19 +02:00 |
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Florent Kermarrec
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ad9ecdbd5e
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use udp port 1234 for etherbone
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2017-06-22 11:28:45 +02:00 |
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Florent Kermarrec
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e68e2ed73c
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frontend/etherbone: add description
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2017-04-26 23:43:43 +02:00 |
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Florent Kermarrec
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f6d8ddbba0
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update litex uart
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2017-04-19 10:39:52 +02:00 |
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Florent Kermarrec
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62acb5df52
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example_designs: update
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2017-03-30 14:46:54 +02:00 |
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Florent Kermarrec
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42454a5448
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frontend/etherbone: add wishbone slave support (allow extending wishbone bridge over ethernet between boards)
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2017-03-30 14:46:30 +02:00 |
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Florent Kermarrec
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a067691222
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README: update
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2017-01-19 14:53:11 +01:00 |
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Florent Kermarrec
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c4856d1eb5
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test: start converting to python unittest
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2017-01-19 14:33:24 +01:00 |
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Florent Kermarrec
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e1da2df97d
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core/mac/sram: fix reception of frames larger than mtu
-use 32bits length CSR (allow software to detect frames larger than mtu)
-drop remaining bytes larger than mtu
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2016-05-01 07:37:24 +02:00 |
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Florent Kermarrec
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072969ff58
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common: fix eth_mtu (1530 bytes)
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2016-05-01 07:09:37 +02:00 |
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Florent Kermarrec
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94290016d0
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setup.py: fix version (0.1)
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2016-04-29 14:32:05 +02:00 |
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Florent Kermarrec
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33e36dc4d7
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use new Record.connect omit parameter (replace leave_out)
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2016-04-21 08:03:31 +02:00 |
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enjoy-digital
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8590310783
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Merge pull request #2 from mithro/master
Adding a .gitignore file.
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2016-04-19 06:07:22 +02:00 |
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Tim 'mithro' Ansell
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2207cf3cc3
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Adding a .gitignore file.
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2016-04-19 13:02:12 +10:00 |
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Florent Kermarrec
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f55ce1aac6
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core/mac: simplify/improve performance of LiteEthMACSRAMReader
now read data from sram on every clock cycle, allow lower system clock frequency (tested with 50MHz system clock / 125MHz ethernet clock)
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2016-04-03 22:53:02 +02:00 |
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Florent Kermarrec
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c6875b7bff
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example_designs: use new litescope
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2016-03-31 21:27:08 +02:00 |
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Florent Kermarrec
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e006223fee
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test: fix model_tb
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2016-03-31 00:25:50 +02:00 |
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Florent Kermarrec
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de5410429b
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README: we are in 2016
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2016-03-31 00:06:08 +02:00 |
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Florent Kermarrec
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a189b2c195
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phy/s6rgmii: fix missing last signal
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2016-03-29 16:53:37 +02:00 |
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Florent Kermarrec
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b394f2f45e
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test/mac_wishbone_tb: fix simulation
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2016-03-25 12:26:02 +01:00 |
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Florent Kermarrec
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b7f3b3ef42
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test: finish etherbone_tb (simulator limitation removed)
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2016-03-23 09:48:02 +01:00 |
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Florent Kermarrec
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87924c84e6
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test: finish mac_wishbone_tb (simulator limitation removed)
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2016-03-23 09:47:47 +01:00 |
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Florent Kermarrec
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7ea1b5a22d
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test: use passive generators and some cleanup
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2016-03-23 01:42:35 +01:00 |
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Florent Kermarrec
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e73f35c733
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test: remove __init__.py and use setup.py develop
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2016-03-22 10:34:28 +01:00 |
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Florent Kermarrec
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2f15f3748e
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test: use new simulator (still etherbone_tb and mac_wishbone_tb not working due to use of FullMemoryWE)
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2016-03-21 19:59:29 +01:00 |
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Florent Kermarrec
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657ba4cb16
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global: use valid/ready/last signals instead of stb/ack/eop (similar to AXI)
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2016-03-16 21:36:07 +01:00 |
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Florent Kermarrec
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9cd7dc3088
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global: use SyncFIFO instead of Buffer
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2016-03-16 19:45:43 +01:00 |
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Florent Kermarrec
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aff07c6809
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global: use new StrideConverter
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2016-03-16 17:01:13 +01:00 |