Victor Suarez Rovere
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5f14bd4a7f
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add initial support to generate verilog code using wishbone or axi-lite bus standard (depending on the .yml file)
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2022-10-31 20:43:53 -03:00 |
Florent Kermarrec
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b0e7243123
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liteeth_gen: Add data_width support (For 32/8-bit datapath).
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2022-05-16 13:38:05 +02:00 |
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Florent Kermarrec
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ba20fc7b71
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liteeth_gen/udp: Improve flexibility and add support for multiple UDP virtual channels.
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2022-01-28 10:11:45 +01:00 |
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Florent Kermarrec
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680806997d
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liteeth_gen/udp: Directly integrate UDPStreamer to simplify use and just expose a LiteX-Stream/AXI-ST interface.
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2022-01-26 11:18:48 +01:00 |
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Florent Kermarrec
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f264c9d5d5
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liteeth_gen: Add toolchain support/parameter.
LiteX code specialization/generation can be different between toolchain (For the same vendor).
Add parameter to configure it from the .yml file.
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2022-01-26 09:57:43 +01:00 |
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Florent Kermarrec
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53057121e7
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examples: remove old examples and update README (new benches/examples will be added).
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2020-11-23 12:54:09 +01:00 |
Konrad Beckmann
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054eebc25f
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test_etherbone: Fix import of etherbone module
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2020-09-30 21:04:11 +02:00 |
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Florent Kermarrec
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64b85e621e
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add SPDX License identifier to header and specify file is part or LiteEth.
Artix7/Ultrascale 1000BaseX is reused from MiSoC/LiteEthMini, specify it.
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2020-08-23 16:07:12 +02:00 |
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Florent Kermarrec
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1d76d02ea6
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frontend: rename tty to stream (tty was too specific since modules can be used for any kind of data stream).
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2020-07-13 10:08:50 +02:00 |
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Florent Kermarrec
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8e1185711b
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common: remove Port.connect and use 2 separate Record.connect.
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2020-06-22 14:36:44 +02:00 |
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Florent Kermarrec
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92c30489ae
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examples: use CRG from litex.build.
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2020-04-10 10:31:14 +02:00 |
|
Florent Kermarrec
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400ca97f45
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examples: increase clk_freq to 125MHz on udp_s7phyrgmii.yml.
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2020-03-19 22:01:33 +01:00 |
Xiretza
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2e9121d330
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Allow changing all SoC options through YAML config
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2020-03-17 18:52:44 +01:00 |
|
Xiretza
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7a44209f77
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Make memory/CSR regions customizable in config
Also remove interrupt mapping, since it's unused without a CPU anyway.
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2020-02-12 15:55:04 +01:00 |
|
Xiretza
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ca9cbd1555
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Move more options to config file
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2020-02-12 15:55:04 +01:00 |
|
Florent Kermarrec
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358bc23cd4
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examples/.ymls: add separators
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2020-02-12 11:23:33 +01:00 |
|
Florent Kermarrec
|
fcadd60cea
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liteeth/gen: initial switch to YAML config file (similar to LiteDRAM/LitePCIe)
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2020-02-12 00:18:22 +01:00 |
|
Florent Kermarrec
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ddd0431373
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examples: use integrated sram instead of external one. (Also fix regression with new SoC that no longer support address decoders passed to add_wb_slave)
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2020-02-11 21:22:13 +01:00 |
|
Florent Kermarrec
|
bb01840b12
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add initial LiteEth standalone core generator from examples/core.py
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2019-11-24 11:22:51 +01:00 |
|
Florent Kermarrec
|
c1783ce554
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examples/targets: update and cleanup
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2019-11-23 19:49:23 +01:00 |
|
Florent Kermarrec
|
d3b2f3d361
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examples/targets: udpate analyzer
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2019-11-23 15:47:42 +01:00 |
|
Florent Kermarrec
|
dc8ddf6895
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examples: keep up to date with LiteX
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2019-11-23 15:23:24 +01:00 |
|
Florent Kermarrec
|
e980b603cc
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example/udp_loopback: simplify/cleanup and make it more generic
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2019-11-20 08:53:16 +01:00 |
Yehowshua Immanuel
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50cc7d0671
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examples: add practical UDP loopback example with Versa ECP5
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2019-11-20 08:18:50 +01:00 |
|
Florent Kermarrec
|
4bc79cefd8
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examples/targets/core: update
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2019-09-24 12:53:06 +02:00 |
|
Florent Kermarrec
|
ad187d35f2
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add CONTRIBUTORS file and add copyright header to all files
|
2019-06-24 11:43:10 +02:00 |
|
Florent Kermarrec
|
fd6d6c30ba
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mac: update imports
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2019-06-24 11:23:13 +02:00 |
|
Florent Kermarrec
|
40b99ecc05
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test: use new RemoteClient import
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2018-09-23 10:28:50 +02:00 |
|
Florent Kermarrec
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94af3d63d9
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README: update and rename example_designs to examples
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2018-08-31 08:26:37 +02:00 |