cb27987b8c
examples/make: look for platform in migen if not present in litex
2018-09-21 07:52:29 +02:00
686db4f3cd
Merge pull request #12 from xobs/default-length
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analyzer-driver: use default depth from config
2018-09-13 14:38:56 +02:00
4f8b9a3567
analyzer-driver: use default depth from config
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The configuration already knows what the default depth is, so just use
the default depth from there.
Also set the default offset to 0, since that is frequently a good default.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-09-13 13:48:09 +08:00
7c1c62e34a
README: update and rename example_designs to examples
2018-08-31 08:34:09 +02:00
3567b68981
dump/vcd: fix code generation
2018-08-30 14:39:09 +02:00
182b683586
core: change cd parameter to clock_domain (keep retro compatibility for now)
2018-08-28 11:58:44 +02:00
f26e36ef23
Merge pull request #11 from xobs/add-trigger-depth
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add trigger depth option
2018-08-02 10:49:50 +02:00
71ffaa7484
add trigger depth option
2018-08-02 11:01:44 +08:00
bfd06f819e
core: add FSM support (and example)
2018-07-20 09:36:42 +02:00
2ca58e488f
setup.py: fix exclude, add example_designs to exclude
2018-07-19 11:29:52 +02:00
cd63a43393
setup.py: exclude sim, test, doc directories
2018-07-18 09:43:23 +02:00
f03345d9f0
software/driver/analyzer: add get_instant_value to get instant value of one signal
2018-06-08 09:07:06 +02:00
af5bfd131f
software/driver/analyzer: add assertions
2018-06-04 10:10:03 +02:00
3efaefaae2
example_designs: typo
2018-06-04 08:04:10 +02:00
d919f90cf6
core: use bits_for(n) instead of max=n on Mux (fix case with only one group of signals)
2018-05-31 09:32:22 +02:00
6289e81b81
example_designs: demonstrate new features
2018-05-28 23:43:44 +02:00
e92f0b7ea2
example_designs/test: cleanup and simplify
2018-05-28 23:12:47 +02:00
2233bc290e
core: another cleanup/simplify pass
2018-05-28 23:12:15 +02:00
a269e67a10
software: add rising/falling edge support
2018-05-28 19:42:46 +02:00
65b7f08cbc
core: add full flag for trigger memory
2018-05-28 19:41:44 +02:00
c0bab06765
core: add sequential-triggering and simplify control
2018-05-28 19:16:53 +02:00
26a8b8989b
example_designs: update
2018-05-28 18:05:31 +02:00
8d4c1ddcf9
core: simplify and run storage in "scope" clock domain to get rid of cd_ratio.
2018-05-28 18:05:05 +02:00
9d5e605df3
replace litex.gen imports with migen imports
2018-02-23 13:43:47 +01:00
302a484697
bump to 0.2.dev
2018-02-23 13:43:28 +01:00
62c4bdd102
uniformize litex cores
2018-02-22 10:18:17 +01:00
985585f0b9
__init__: add LiteScopeIODriver and LiteScopeAnalyzerDriver imports
2018-02-19 14:50:03 +01:00
aa44da35c6
example_designs/make.py: fix typos
2018-01-20 21:22:28 +01:00
72e71e7200
core: simplify
2018-01-20 12:43:16 +01:00
7803591050
Merge pull request #9 from felixheld/indentation-fixes
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Fix all remaining indentation issues in python code
2018-01-13 13:33:11 +11:00
febb358d33
Fix all remaining indentation issues in python code
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I ran a script that shouldn't have missed any tab in the python source files.
2018-01-13 13:24:29 +11:00
7757727f5b
implement memory flush in hardware instead of software
2017-11-17 15:11:03 +01:00
c6c0812e62
doc: add simple architecture diagram
2017-11-13 20:39:14 +01:00
d5887a3eb0
example_designs: keep up to date with litex
2017-09-25 12:54:25 +02:00
d4d63d7474
software/driver/analyzer: fix groups build
2017-07-24 22:57:19 +02:00
8d87992b95
litescope/software/dump/sigrok: remove 8 bits limitation and some cleanup
2017-06-23 11:40:44 +02:00
d8649fca5f
software/dump/sigrok: add limitation to 8 bits, will be fixed later
2017-06-23 10:50:08 +02:00
2048acf80e
software/dump/sigrok: fix write_data, now working :)
2017-06-23 08:57:10 +02:00
3d35e72a48
software/driver/analyzer: fix wait_done
2017-06-22 19:24:08 +02:00
dff7ac8d4e
software/dump/sigrok: rename capture file to dump
2017-06-22 19:20:34 +02:00
b57a5f9369
example_design: demonstrate how to use groups, create separate capture for vcd (bus support) and sigrok (no bus support)
2017-06-22 19:12:33 +02:00
92710208de
software/driver/analyzer: add wait_done method
2017-06-22 19:11:11 +02:00
0c4d0f4505
software/dump/sigrok: fix samplerate generation (2x since we are doubling data to show capture clk)
2017-06-22 18:45:15 +02:00
f8ea15363c
software/dump/common: rename clk to capture_clk in dumps
2017-06-22 18:41:08 +02:00
49c524d866
software/driver: remove samplerate handling and simply pass it when writing dump if wanted
2017-06-22 18:37:54 +02:00
9e669dce7f
software/driver/analyzer: add upload progress bar and improve presentation
2017-06-22 18:19:44 +02:00
1f33e44ad5
software/driver/io: cleanup
2017-06-22 18:13:07 +02:00
01eabb2d0d
example_design: update with litex and fix
2017-06-22 17:58:19 +02:00
e2cb7bd829
README: consistency between projects
2017-06-22 17:00:16 +02:00
cf7ea12ec8
litescope: add support for groups of signals and dynamic muxing between them
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allow multiple debug configuration in a single bitstream
2017-06-09 12:14:00 +02:00
Florent Kermarrec
Sean Cross
bunnie
Tim Ansell
Felix Held