2021-10-13 06:18:46 -04:00
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Franck Jullien <franck.jullien@collshade.fr>
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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2024-09-03 10:01:51 -04:00
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import time
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2021-10-13 06:18:46 -04:00
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from migen import *
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2021-10-13 10:35:14 -04:00
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from migen.genlib.resetsync import AsyncResetSynchronizer
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2023-02-23 03:09:33 -05:00
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from litex.gen import *
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2022-10-28 04:35:57 -04:00
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2021-10-13 06:18:46 -04:00
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from litex_boards.platforms import efinix_trion_t120_bga576_dev_kit
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2021-10-14 09:36:14 -04:00
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.interconnect import axi
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2021-11-09 05:32:32 -05:00
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from liteeth.phy.trionrgmii import LiteEthPHYRGMII
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2021-10-13 06:18:46 -04:00
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# CRG ----------------------------------------------------------------------------------------------
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2022-10-27 10:58:55 -04:00
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class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
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#self.rst = Signal()
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self.cd_sys = ClockDomain()
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# # #
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clk40 = platform.request("clk40")
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rst_n = platform.request("user_btn", 0)
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# PLL
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self.pll = pll = TRIONPLL(platform)
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#self.comb += pll.reset.eq(~rst_n | self.rst)
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self.comb += pll.reset.eq(~rst_n)
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pll.register_clkin(clk40, 40e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True, name="axi_clk")
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=75e6,
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with_spi_flash = False,
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with_ethernet = False,
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with_etherbone = False,
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eth_phy = 0,
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eth_rmii_pmod = True,
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eth_ip = "192.168.1.50",
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remote_ip = None,
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with_led_chaser = True,
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**kwargs):
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platform = efinix_trion_t120_bga576_dev_kit.Platform()
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2021-10-14 04:10:42 -04:00
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# USBUART PMOD as Serial--------------------------------------------------------------------
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platform.add_extension(efinix_trion_t120_bga576_dev_kit.usb_pmod_io("pmod_e"))
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kwargs["uart_name"] = "usb_uart"
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# CRG --------------------------------------------------------------------------------------
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self.crg = _CRG(platform, sys_clk_freq)
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2022-04-21 06:17:26 -04:00
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Efinix Trion T120 BGA576 Dev Kit", **kwargs)
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2021-10-14 13:16:01 -04:00
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# SPI Flash --------------------------------------------------------------------------------
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if with_spi_flash:
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from litespi.modules import W25Q128JV
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="4x", module=W25Q128JV(Codes.READ_1_1_4), with_master=True)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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2021-10-25 12:35:35 -04:00
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# Tristate Test ----------------------------------------------------------------------------
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from litex.build.generic_platform import Subsignal, Pins, Misc, IOStandard
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from litex.soc.cores.bitbang import I2CMaster
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platform.add_extension([("i2c", 0,
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Subsignal("sda", Pins("T12")),
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Subsignal("scl", Pins("V11")),
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IOStandard("3.3_V_LVTTL_/_LVCMOS"),
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)])
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self.i2c = I2CMaster(pads=platform.request("i2c"))
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2021-11-09 05:32:32 -05:00
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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# Use board's Ethernet PHYs.
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if not eth_rmii_pmod:
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msg = "\n"
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msg += "rx_ctl/tx_ctl pads location aren't compatible with DDIO mode.\n"
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msg += "An hardware modification must be done:\n"
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msg += "- rx_ctl: a wire must be soldered between R120 and R174\n"
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msg += "- tx_ctl: a wire must be soldered between ETH1_TXEN (Pad 30) and R173\n"
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print(msg)
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time.sleep(2)
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self.ethphy = LiteEthPHYRGMII(
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platform = platform,
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clock_pads = platform.request("eth_clocks", eth_phy),
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pads = platform.request("eth", eth_phy),
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with_hw_init_reset = False)
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# Use Ethernet RMII PMOD.
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else:
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from litex.build.generic_platform import Pins, Subsignal, IOStandard
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def eth_lan8720_rmii_pmod_io(pmod):
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# Lan8020 RMII PHY "PMOD": To be used as a PMOD, MDIO should be disconnected and TX1 connected to PMOD8 IO.
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return [
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("eth_rmii_clocks", 0,
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Subsignal("ref_clk", Pins(f"{pmod}:6")),
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IOStandard("3.3_V_LVTTL_/_LVCMOS"),
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),
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("eth_rmii", 0,
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Subsignal("rx_data", Pins(f"{pmod}:5 {pmod}:1")),
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Subsignal("crs_dv", Pins(f"{pmod}:2")),
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Subsignal("tx_en", Pins(f"{pmod}:4")),
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Subsignal("tx_data", Pins(f"{pmod}:0 {pmod}:7")),
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IOStandard("3.3_V_LVTTL_/_LVCMOS")
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),
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]
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platform.add_extension(eth_lan8720_rmii_pmod_io("pmod_d"))
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from liteeth.phy.rmii import LiteEthPHYRMII
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self.ethphy = LiteEthPHYRMII(
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clock_pads = platform.request("eth_rmii_clocks"),
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pads = platform.request("eth_rmii"),
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refclk_cd = None
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)
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2021-11-09 05:32:32 -05:00
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy, local_ip=eth_ip, remote_ip=remote_ip, software_debug=False)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
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2021-11-09 10:13:40 -05:00
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# LPDDR3 SDRAM -----------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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# DRAM / PLL Blocks.
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# ------------------
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dram_pll_refclk = platform.request("dram_pll_refclk")
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platform.toolchain.excluded_ios.append(dram_pll_refclk)
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self.platform.toolchain.additional_sdc_commands.append(f"create_clock -period {1e9/50e6} dram_pll_refclk")
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2021-11-16 11:41:26 -05:00
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from litex.build.efinix import InterfaceWriterBlock, InterfaceWriterXMLBlock
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import xml.etree.ElementTree as et
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class PLLDRAMBlock(InterfaceWriterBlock):
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@staticmethod
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def generate():
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return """
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design.create_block("dram_pll", block_type="PLL")
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design.set_property("dram_pll", {"REFCLK_FREQ":"50.0"}, block_type="PLL")
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design.gen_pll_ref_clock("dram_pll", pll_res="PLL_BR0", refclk_src="EXTERNAL", refclk_name="dram_pll_clkin", ext_refclk_no="0")
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design.set_property("dram_pll","LOCKED_PIN","dram_pll_locked", block_type="PLL")
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design.set_property("dram_pll","RSTN_PIN","dram_pll_rst_n", block_type="PLL")
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design.set_property("dram_pll", {"CLKOUT0_PIN" : "dram_pll_CLKOUT0"}, block_type="PLL")
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design.set_property("dram_pll","CLKOUT0_PHASE","0","PLL")
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calc_result = design.auto_calc_pll_clock("dram_pll", {"CLKOUT0_FREQ": "400.0"})
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"""
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platform.toolchain.ifacewriter.blocks.append(PLLDRAMBlock())
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class DRAMXMLBlock(InterfaceWriterXMLBlock):
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@staticmethod
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def generate(root, namespaces):
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# CHECKME: Switch to DDRDesignService?
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ddr_info = root.find("efxpt:ddr_info", namespaces)
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ddr = et.SubElement(ddr_info, "efxpt:ddr",
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name = "ddr_inst1",
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ddr_def = "DDR_0",
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cs_preset_id = "173",
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cs_mem_type = "LPDDR3",
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cs_ctrl_width = "x32",
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cs_dram_width = "x32",
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cs_dram_density = "8G",
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cs_speedbin = "800",
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target0_enable = "true",
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target1_enable = "true",
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ctrl_type = "none"
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)
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gen_pin_target0 = et.SubElement(ddr, "efxpt:gen_pin_target0")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_wdata", type_name=f"WDATA_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_wready", type_name=f"WREADY_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_wid", type_name=f"WID_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_bready", type_name=f"BREADY_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_rdata", type_name=f"RDATA_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_aid", type_name=f"AID_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_bvalid", type_name=f"BVALID_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_rlast", type_name=f"RLAST_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_bid", type_name=f"BID_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_asize", type_name=f"ASIZE_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_atype", type_name=f"ATYPE_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_aburst", type_name=f"ABURST_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_wvalid", type_name=f"WVALID_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_wlast", type_name=f"WLAST_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_aaddr", type_name=f"AADDR_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_rid", type_name=f"RID_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_avalid", type_name=f"AVALID_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_rvalid", type_name=f"RVALID_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_alock", type_name=f"ALOCK_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_rready", type_name=f"RREADY_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_rresp", type_name=f"RRESP_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_wstrb", type_name=f"WSTRB_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_aready", type_name=f"AREADY_0", is_bus="false")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi0_alen", type_name=f"ALEN_0", is_bus="true")
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et.SubElement(gen_pin_target0, "efxpt:pin", name="axi_clk", type_name=f"ACLK_0", is_bus="false", is_clk="true", is_clk_invert="false")
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gen_pin_target1 = et.SubElement(ddr, "efxpt:gen_pin_target1")
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et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_wdata", type_name=f"WDATA_1", is_bus="true")
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et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_wready", type_name=f"WREADY_1", is_bus="false")
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et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_wid", type_name=f"WID_1", is_bus="true")
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et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_bready", type_name=f"BREADY_1", is_bus="false")
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et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_rdata", type_name=f"RDATA_1", is_bus="true")
|
|
|
|
|
et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_aid", type_name=f"AID_1", is_bus="true")
|
|
|
|
|
et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_bvalid", type_name=f"BVALID_1", is_bus="false")
|
|
|
|
|
et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_rlast", type_name=f"RLAST_1", is_bus="false")
|
|
|
|
|
et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_bid", type_name=f"BID_1", is_bus="true")
|
|
|
|
|
et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_asize", type_name=f"ASIZE_1", is_bus="true")
|
|
|
|
|
et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_atype", type_name=f"ATYPE_1", is_bus="false")
|
|
|
|
|
et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_aburst", type_name=f"ABURST_1", is_bus="true")
|
|
|
|
|
et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_wvalid", type_name=f"WVALID_1", is_bus="false")
|
|
|
|
|
et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_wlast", type_name=f"WLAST_1", is_bus="false")
|
|
|
|
|
et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_aaddr", type_name=f"AADDR_1", is_bus="true")
|
|
|
|
|
et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_rid", type_name=f"RID_1", is_bus="true")
|
|
|
|
|
et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_avalid", type_name=f"AVALID_1", is_bus="false")
|
|
|
|
|
et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_rvalid", type_name=f"RVALID_1", is_bus="false")
|
|
|
|
|
et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_alock", type_name=f"ALOCK_1", is_bus="true")
|
|
|
|
|
et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_rready", type_name=f"RREADY_1", is_bus="false")
|
|
|
|
|
et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_rresp", type_name=f"RRESP_1", is_bus="true")
|
|
|
|
|
et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_wstrb", type_name=f"WSTRB_1", is_bus="true")
|
|
|
|
|
et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_aready", type_name=f"AREADY_1", is_bus="false")
|
|
|
|
|
et.SubElement(gen_pin_target1, "efxpt:pin", name="axi1_alen", type_name=f"ALEN_1", is_bus="true")
|
|
|
|
|
et.SubElement(gen_pin_target1, "efxpt:pin", name="axi_clk", type_name=f"ACLK_1", is_bus="false", is_clk="true", is_clk_invert="false")
|
|
|
|
|
|
|
|
|
|
gen_pin_config = et.SubElement(ddr, "efxpt:gen_pin_config")
|
2021-11-16 11:50:47 -05:00
|
|
|
et.SubElement(gen_pin_config, "efxpt:pin", name="", type_name="CFG_SEQ_RST", is_bus="false")
|
|
|
|
|
et.SubElement(gen_pin_config, "efxpt:pin", name="", type_name="CFG_SCL_IN", is_bus="false")
|
|
|
|
|
et.SubElement(gen_pin_config, "efxpt:pin", name="", type_name="CFG_SEQ_START", is_bus="false")
|
|
|
|
|
et.SubElement(gen_pin_config, "efxpt:pin", name="", type_name="RSTN", is_bus="false")
|
|
|
|
|
et.SubElement(gen_pin_config, "efxpt:pin", name="", type_name="CFG_SDA_IN", is_bus="false")
|
|
|
|
|
et.SubElement(gen_pin_config, "efxpt:pin", name="", type_name="CFG_SDA_OEN", is_bus="false")
|
2021-11-16 11:41:26 -05:00
|
|
|
|
|
|
|
|
cs_fpga = et.SubElement(ddr, "efxpt:cs_fpga")
|
|
|
|
|
et.SubElement(cs_fpga, "efxpt:param", name="FPGA_ITERM", value="120", value_type="str")
|
|
|
|
|
et.SubElement(cs_fpga, "efxpt:param", name="FPGA_OTERM", value="34", value_type="str")
|
|
|
|
|
|
|
|
|
|
cs_memory = et.SubElement(ddr, "efxpt:cs_memory")
|
|
|
|
|
et.SubElement(cs_memory, "efxpt:param", name="RTT_NOM", value="RZQ/2", value_type="str")
|
|
|
|
|
et.SubElement(cs_memory, "efxpt:param", name="MEM_OTERM", value="40", value_type="str")
|
|
|
|
|
et.SubElement(cs_memory, "efxpt:param", name="CL", value="RL=6/WL=3", value_type="str")
|
|
|
|
|
|
|
|
|
|
timing = et.SubElement(ddr, "efxpt:cs_memory_timing")
|
|
|
|
|
et.SubElement(timing, "efxpt:param", name="tRAS", value="42.000", value_type="float")
|
|
|
|
|
et.SubElement(timing, "efxpt:param", name="tRC", value="60.000", value_type="float")
|
|
|
|
|
et.SubElement(timing, "efxpt:param", name="tRP", value="18.000", value_type="float")
|
|
|
|
|
et.SubElement(timing, "efxpt:param", name="tRCD", value="18.000", value_type="float")
|
|
|
|
|
et.SubElement(timing, "efxpt:param", name="tREFI", value="3.900", value_type="float")
|
|
|
|
|
et.SubElement(timing, "efxpt:param", name="tRFC", value="210.000", value_type="float")
|
|
|
|
|
et.SubElement(timing, "efxpt:param", name="tRTP", value="10.000", value_type="float")
|
|
|
|
|
et.SubElement(timing, "efxpt:param", name="tWTR", value="10.000", value_type="float")
|
|
|
|
|
et.SubElement(timing, "efxpt:param", name="tRRD", value="10.000", value_type="float")
|
|
|
|
|
et.SubElement(timing, "efxpt:param", name="tFAW", value="50.000", value_type="float")
|
|
|
|
|
|
|
|
|
|
cs_control = et.SubElement(ddr, "efxpt:cs_control")
|
|
|
|
|
et.SubElement(cs_control, "efxpt:param", name="AMAP", value="ROW-COL_HIGH-BANK-COL_LOW", value_type="str")
|
|
|
|
|
et.SubElement(cs_control, "efxpt:param", name="EN_AUTO_PWR_DN", value="Off", value_type="str")
|
|
|
|
|
et.SubElement(cs_control, "efxpt:param", name="EN_AUTO_SELF_REF", value="No", value_type="str")
|
|
|
|
|
|
|
|
|
|
cs_gate_delay = et.SubElement(ddr, "efxpt:cs_gate_delay")
|
|
|
|
|
et.SubElement(cs_gate_delay, "efxpt:param", name="EN_DLY_OVR", value="No", value_type="str")
|
|
|
|
|
et.SubElement(cs_gate_delay, "efxpt:param", name="GATE_C_DLY", value="3", value_type="int")
|
|
|
|
|
et.SubElement(cs_gate_delay, "efxpt:param", name="GATE_F_DLY", value="0", value_type="int")
|
|
|
|
|
|
|
|
|
|
platform.toolchain.ifacewriter.xml_blocks.append(DRAMXMLBlock())
|
2021-11-10 06:07:30 -05:00
|
|
|
|
|
|
|
|
# DRAM Rst.
|
|
|
|
|
# ---------
|
2021-11-12 13:43:28 -05:00
|
|
|
dram_pll_rst_n = platform.add_iface_io("dram_pll_rst_n")
|
|
|
|
|
self.comb += dram_pll_rst_n.eq(platform.request("user_btn", 1))
|
2021-11-10 06:07:30 -05:00
|
|
|
|
2021-11-16 12:12:42 -05:00
|
|
|
# DRAM AXI-Ports.
|
2021-11-10 06:07:30 -05:00
|
|
|
# --------------
|
2021-11-16 12:12:42 -05:00
|
|
|
for n, data_width in {
|
|
|
|
|
0: 256, # target0: 256-bit.
|
|
|
|
|
1: 128, # target1: 128-bit
|
|
|
|
|
}.items():
|
|
|
|
|
axi_port = axi.AXIInterface(data_width=data_width, address_width=28, id_width=8) # 256MB.
|
|
|
|
|
ios = [(f"axi{n}", 0,
|
|
|
|
|
Subsignal("wdata", Pins(data_width)),
|
|
|
|
|
Subsignal("wready", Pins(1)),
|
|
|
|
|
Subsignal("wid", Pins(8)),
|
|
|
|
|
Subsignal("bready", Pins(1)),
|
|
|
|
|
Subsignal("rdata", Pins(data_width)),
|
|
|
|
|
Subsignal("aid", Pins(8)),
|
|
|
|
|
Subsignal("bvalid", Pins(1)),
|
|
|
|
|
Subsignal("rlast", Pins(1)),
|
|
|
|
|
Subsignal("bid", Pins(8)),
|
|
|
|
|
Subsignal("asize", Pins(3)),
|
|
|
|
|
Subsignal("atype", Pins(1)),
|
|
|
|
|
Subsignal("aburst", Pins(2)),
|
|
|
|
|
Subsignal("wvalid", Pins(1)),
|
|
|
|
|
Subsignal("aaddr", Pins(32)),
|
|
|
|
|
Subsignal("rid", Pins(8)),
|
|
|
|
|
Subsignal("avalid", Pins(1)),
|
|
|
|
|
Subsignal("rvalid", Pins(1)),
|
|
|
|
|
Subsignal("alock", Pins(2)),
|
|
|
|
|
Subsignal("rready", Pins(1)),
|
|
|
|
|
Subsignal("rresp", Pins(2)),
|
|
|
|
|
Subsignal("wstrb", Pins(data_width//8)),
|
|
|
|
|
Subsignal("aready", Pins(1)),
|
|
|
|
|
Subsignal("alen", Pins(8)),
|
|
|
|
|
Subsignal("wlast", Pins(1)),
|
|
|
|
|
)]
|
|
|
|
|
io = platform.add_iface_ios(ios)
|
|
|
|
|
rw_n = axi_port.ar.valid
|
|
|
|
|
self.comb += [
|
|
|
|
|
# Pseudo AW/AR Channels.
|
|
|
|
|
io.atype.eq(~rw_n),
|
|
|
|
|
io.aaddr.eq( Mux(rw_n, axi_port.ar.addr, axi_port.aw.addr)),
|
|
|
|
|
io.aid.eq( Mux(rw_n, axi_port.ar.id, axi_port.aw.id)),
|
|
|
|
|
io.alen.eq( Mux(rw_n, axi_port.ar.len, axi_port.aw.len)),
|
|
|
|
|
io.asize.eq( Mux(rw_n, axi_port.ar.size, axi_port.aw.size)),
|
|
|
|
|
io.aburst.eq( Mux(rw_n, axi_port.ar.burst, axi_port.aw.burst)),
|
|
|
|
|
io.alock.eq( Mux(rw_n, axi_port.ar.lock, axi_port.aw.lock)),
|
|
|
|
|
io.avalid.eq( Mux(rw_n, axi_port.ar.valid, axi_port.aw.valid)),
|
|
|
|
|
axi_port.aw.ready.eq(~rw_n & io.aready),
|
|
|
|
|
axi_port.ar.ready.eq( rw_n & io.aready),
|
|
|
|
|
|
|
|
|
|
# R Channel.
|
|
|
|
|
axi_port.r.id.eq(io.rid),
|
|
|
|
|
axi_port.r.data.eq(io.rdata),
|
|
|
|
|
axi_port.r.last.eq(io.rlast),
|
|
|
|
|
axi_port.r.resp.eq(io.rresp),
|
|
|
|
|
axi_port.r.valid.eq(io.rvalid),
|
|
|
|
|
io.rready.eq(axi_port.r.ready),
|
|
|
|
|
|
|
|
|
|
# W Channel.
|
|
|
|
|
io.wid.eq(axi_port.w.id),
|
|
|
|
|
io.wstrb.eq(axi_port.w.strb),
|
|
|
|
|
io.wdata.eq(axi_port.w.data),
|
|
|
|
|
io.wlast.eq(axi_port.w.last),
|
|
|
|
|
io.wvalid.eq(axi_port.w.valid),
|
|
|
|
|
axi_port.w.ready.eq(io.wready),
|
|
|
|
|
|
|
|
|
|
# B Channel.
|
|
|
|
|
axi_port.b.id.eq(io.bid),
|
|
|
|
|
axi_port.b.valid.eq(io.bvalid),
|
|
|
|
|
io.bready.eq(axi_port.b.ready),
|
|
|
|
|
]
|
|
|
|
|
|
|
|
|
|
# Connect AXI interface to the main bus of the SoC.
|
|
|
|
|
axi_lite_port = axi.AXILiteInterface(data_width=data_width, address_width=28)
|
|
|
|
|
self.submodules += axi.AXILite2AXI(axi_lite_port, axi_port)
|
|
|
|
|
self.bus.add_slave(f"target{n}", axi_lite_port, SoCRegion(origin=0x4000_0000 + 0x1000_0000*n, size=0x1000_0000)) # 256MB.
|
|
|
|
|
|
2023-07-27 05:52:40 -04:00
|
|
|
# Use DRAM's target0 port as Main Ram -----------------------------------------------------
|
|
|
|
|
self.bus.add_region("main_ram", SoCRegion(
|
|
|
|
|
origin = 0x4000_0000,
|
|
|
|
|
size = 0x1000_0000, # 256MB.
|
|
|
|
|
linker = True)
|
|
|
|
|
)
|
2021-11-09 10:13:40 -05:00
|
|
|
|
2021-10-13 06:18:46 -04:00
|
|
|
# Build --------------------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
|
|
def main():
|
2022-11-06 15:39:52 -05:00
|
|
|
from litex.build.parser import LiteXArgumentParser
|
2022-11-08 04:41:35 -05:00
|
|
|
parser = LiteXArgumentParser(platform=efinix_trion_t120_bga576_dev_kit.Platform, description="LiteX SoC on Efinix Trion T120 BGA576 Dev Kit.")
|
|
|
|
|
parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.")
|
|
|
|
|
parser.add_target_argument("--sys-clk-freq", default=75e6, type=float, help="System clock frequency.")
|
|
|
|
|
parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
|
2022-11-05 03:07:14 -04:00
|
|
|
ethopts = parser.target_group.add_mutually_exclusive_group()
|
2024-09-03 06:42:49 -04:00
|
|
|
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
|
|
|
|
|
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
|
|
|
|
|
parser.add_target_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.")
|
|
|
|
|
parser.add_target_argument("--remote-ip", default="192.168.1.100", help="Remote IP address of TFTP server.")
|
|
|
|
|
parser.add_target_argument("--eth-phy", default=0, type=int, help="Ethernet PHY: 0 (default) or 1.")
|
2021-10-13 06:18:46 -04:00
|
|
|
args = parser.parse_args()
|
|
|
|
|
|
2021-11-09 05:32:32 -05:00
|
|
|
soc = BaseSoC(
|
2022-11-08 04:41:35 -05:00
|
|
|
sys_clk_freq = args.sys_clk_freq,
|
2021-10-14 13:16:01 -04:00
|
|
|
with_spi_flash = args.with_spi_flash,
|
2021-11-09 05:32:32 -05:00
|
|
|
with_ethernet = args.with_ethernet,
|
|
|
|
|
with_etherbone = args.with_etherbone,
|
|
|
|
|
eth_ip = args.eth_ip,
|
2024-09-03 06:42:49 -04:00
|
|
|
remote_ip = args.remote_ip,
|
2021-11-09 05:32:32 -05:00
|
|
|
eth_phy = args.eth_phy,
|
2022-11-07 02:43:26 -05:00
|
|
|
**parser.soc_argdict)
|
2022-11-05 03:07:14 -04:00
|
|
|
builder = Builder(soc, **parser.builder_argdict)
|
2022-05-06 09:14:32 -04:00
|
|
|
if args.build:
|
2022-11-05 03:07:14 -04:00
|
|
|
builder.build(**parser.toolchain_argdict)
|
2021-10-13 06:18:46 -04:00
|
|
|
|
|
|
|
|
if args.load:
|
|
|
|
|
prog = soc.platform.create_programmer()
|
2022-03-17 04:21:05 -04:00
|
|
|
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
|
2021-10-13 06:18:46 -04:00
|
|
|
|
2021-10-15 03:38:43 -04:00
|
|
|
if args.flash:
|
|
|
|
|
from litex.build.openfpgaloader import OpenFPGALoader
|
|
|
|
|
prog = OpenFPGALoader("trion_t120_bga576")
|
2022-03-17 04:21:05 -04:00
|
|
|
prog.flash(0, builder.get_bitstream_filename(mode="flash", ext=".hex")) # FIXME
|
2021-10-15 03:38:43 -04:00
|
|
|
|
2021-10-13 06:18:46 -04:00
|
|
|
if __name__ == "__main__":
|
|
|
|
|
main()
|
