litex-boards/litex_boards/targets/linsn_rv901t.py

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#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
from litex.gen import LiteXModule
from litex.build.io import DDROutput
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from litex_boards.platforms import linsn_rv901t
from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
from litex.soc.cores.clock import S6PLL
from litex.soc.cores.led import LedChaser
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from litedram.modules import M12L64322A
from litedram.phy import GENSDRPHY
from liteeth.phy.s6rgmii import LiteEthPHYRGMII
# CRG ----------------------------------------------------------------------------------------------
class _CRG(LiteXModule):
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def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.cd_sys = ClockDomain()
self.cd_sys_ps = ClockDomain()
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# # #
clk25 = platform.request("clk25")
self.pll = pll = S6PLL(speedgrade=-2)
self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk25, 25e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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# SDRAM clock
self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
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# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=75e6,
with_ethernet = False,
with_etherbone = False,
eth_phy = 0,
with_led_chaser = True,
**kwargs):
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platform = linsn_rv901t.Platform()
# CRG --------------------------------------------------------------------------------------
self.crg = _CRG(platform, sys_clk_freq)
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# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Linsn RV901T", **kwargs)
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# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram",
phy = self.sdrphy,
module = M12L64322A(sys_clk_freq, "1:1"),
l2_cache_size = kwargs.get("l2_size", 8192)
)
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# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks", eth_phy),
pads = self.platform.request("eth", eth_phy),
tx_delay = 0e-9)
if with_ethernet:
self.add_ethernet(phy=self.ethphy, with_timing_constraints=False)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, with_timing_constraints=False)
# Timing Constraints.
platform.add_period_constraint(platform.lookup_request("eth_clocks", eth_phy).rx, 1e9/125e6)
platform.add_false_path_constraints(self.crg.cd_sys.clk, platform.lookup_request("eth_clocks", eth_phy).rx)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
def main():
from litex.build.parser import LiteXArgumentParser
parser = LiteXArgumentParser(platform=linsn_rv901t.Platform, description="LiteX SoC on Linsn RV901T.")
parser.add_target_argument("--sys-clk-freq", default=75e6, type=float, help="System clock frequency.")
ethopts = parser.target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
parser.add_target_argument("--eth-phy", default=0, type=int, help="Ethernet PHY (0 or 1).")
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args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = args.sys_clk_freq,
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
eth_phy = int(args.eth_phy),
**parser.soc_argdict
)
builder = Builder(soc, **parser.builder_argdict)
if args.build:
builder.build(**parser.toolchain_argdict)
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if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
main()