2019-07-12 13:19:01 -04:00
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# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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2019-06-10 11:09:51 -04:00
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# License: BSD
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from litex.build.generic_platform import *
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from litex.build.microsemi import MicrosemiPlatform
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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("clk50", 0, Pins("R1"), IOStandard("LVCMOS25")),
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("clk50", 1, Pins("J3"), IOStandard("LVCMOS25")),
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("rst_n", 0, Pins("F5"), IOStandard("LVCMOS33")),
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("user_led", 0, Pins("D6"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("D7"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("D8"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("D9"), IOStandard("LVCMOS33")),
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("user_btn", 0, Pins("E13"), IOStandard("LVCMOS33")),
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("user_btn", 1, Pins("E14"), IOStandard("LVCMOS33")),
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("serial", 0,
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Subsignal("tx", Pins("F17")),
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Subsignal("rx", Pins("F16")),
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IOStandard("LVCMOS33")
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),
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("spiflash4x", 0,
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Subsignal("clk", Pins("J1")),
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Subsignal("cs_n", Pins("H1")),
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Subsignal("dq", Pins("F2 F1 M7 M8")),
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IOStandard("LVCMOS25")
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),
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("spiflash", 0,
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Subsignal("clk", Pins("J1")),
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Subsignal("cs_n", Pins("H1")),
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Subsignal("mosi", Pins("F2")),
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Subsignal("miso", Pins("F1")),
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Subsignal("wp", Pins("M7")),
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Subsignal("hold", Pins("M8")),
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IOStandard("LVCMOS25"),
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),
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("ddram", 0,
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Subsignal("a", Pins(
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"U5 U4 V4 W3 V5 W4 Y3 AA3",
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"Y4 Y5 AA2 AB2 V6 W6 AB3"),
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IOStandard("SSTL15II")),
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Subsignal("ba", Pins("V7 Y6 U7"), IOStandard("SSTL15II")),
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Subsignal("ras_n", Pins("AA6"), IOStandard("SSTL15II")),
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Subsignal("cas_n", Pins("AA5"), IOStandard("SSTL15II")),
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Subsignal("we_n", Pins("AB5"), IOStandard("SSTL15II")),
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Subsignal("cs_n", Pins("W7"), IOStandard("SSTL15II")),
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Subsignal("dm", Pins("Y9 R15"), IOStandard("SSTL15II")),
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Subsignal("dq", Pins(
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"T7 T8 U8 U9 R10 V9 V10 W9",
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"V14 U14 R12 T11 U15 T13 U13 T15"),
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IOStandard("SSTL15II")),
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Subsignal("dqs_p", Pins("T10 R13"), IOStandard("SSTL15II")),
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Subsignal("dqs_n", Pins("U10 T12"), IOStandard("SSTL15II")),
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Subsignal("clk_p", Pins("V2"), IOStandard("SSTL15II")),
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Subsignal("clk_n", Pins("W2"), IOStandard("SSTL15II")),
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Subsignal("cke", Pins("W8"), IOStandard("SSTL15II")),
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Subsignal("odt", Pins("AA7"), IOStandard("SSTL15II")),
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Subsignal("reset_n", Pins("AB7"), IOStandard("SSTL15II")),
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),
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("eth_clocks", 0,
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Subsignal("tx", Pins("J8")),
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Subsignal("rx", Pins("K3")),
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IOStandard("LVCMOS25")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("L8"), IOStandard("LVCMOS33")),
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Subsignal("int_n", Pins("J4")),
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Subsignal("mdio", Pins("H2")),
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Subsignal("mdc", Pins("J2")),
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Subsignal("rx_ctl", Pins("K5")),
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Subsignal("rx_data", Pins("J9 K1 K6 K4")),
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Subsignal("tx_ctl", Pins("L5")),
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Subsignal("tx_data", Pins("K8 L1 L2 L3")),
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IOStandard("LVCMOS25")
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(MicrosemiPlatform):
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default_clk_name = "clk50"
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default_clk_period = 20.0
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def __init__(self):
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MicrosemiPlatform.__init__(self, "MPF300TS_ES-FCG484-1", _io)
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