2089c2b708
ci: Install meson (now required by picolibc).
2021-09-27 16:21:43 +02:00
f18b10d1ed
Merge pull request #249 from Quiddle11/atlys
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Initial Digilent Atlys support
2021-09-23 10:21:49 +02:00
921c300b50
digilent_atlys: Simplify/Remove entropy...
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Build tested with ./digilent_atlys.py --with-ethernet --build.
2021-09-23 10:17:54 +02:00
7778f1fc93
Merge pull request #272 from alainlou/master
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rz_easyfpga: adjust SDRAM clk phase, also add 1:2 rate
2021-09-23 09:01:17 +02:00
1333f89ed6
rz_easyfpga: adjust SDRAM clk phase
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- also add 1:2 rate
2021-09-22 00:26:28 -04:00
610e82d774
Add initial RZ-EasyFPGA support! ( #270 )
2021-09-21 09:55:22 +02:00
d5eea94289
sispeed_tang_nano_4k: Avoid IOStandard constraints on HyperRAM (Not present in example designs).
2021-09-20 11:46:10 +02:00
5190c9c869
sipeed_tang_nano_4k: Initial Video Out support.
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With colorbars for now, need to free up BRAMS for Video Terminal (or finish HyperRAM support).
2021-09-20 09:32:20 +02:00
30756ce05e
targets: Update to VideoHDMIPHY.
2021-09-20 09:30:32 +02:00
7161ad18ec
sipeed_tang_nano_4k: Integrate new LiteX's GW1NSRPLL.
2021-09-20 08:40:19 +02:00
a5c5ba7652
sipeed_tang_nano_4k: Integrate HyperRam (not yet working).
2021-09-17 16:30:39 +02:00
376a836583
sipeed_tang_nano: Add SPI Flash, Enable CPU and use new external SPI Flash support from OpenFPGALoader.
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./sipeed_tang_nano_4k.py --cpu-type=vexriscv --cpu-variant=lite --build --flash
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2021 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Sep 17 2021 15:54:08
BIOS CRC passed (6cc6de6d)
Migen git sha1: a5bc262
LiteX git sha1: 46cd9c5a
--=============== SoC ==================--
CPU: VexRiscv_Lite @ 27MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 64KiB
SRAM: 8KiB
FLASH: 4096KiB
--========== Initialization ============--
Initializing W25Q32 SPI Flash @0x80000000...
SPI Flash clk configured to 13 MHz
Memspeed at 0x80000000 (Sequential, 4.0KiB)...
Read speed: 1.3MiB/s
Memspeed at 0x80000000 (Random, 4.0KiB)...
Read speed: 521.9KiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex>
2021-09-17 15:57:55 +02:00
28571308bc
sispeed_tang_nano: Add simple UART loopback test... (Not working...)
2021-09-16 19:34:48 +02:00
5955a35372
Add initial Sipeed Tang Nano support (Clk/Leds/Buttons).
2021-09-16 19:22:30 +02:00
c0aed8a727
litex_m2_baseboard: Add Video Terminal support.
2021-09-16 18:54:50 +02:00
32a9256f3b
litex_m2_baseboard: Add SDCard support.
2021-09-16 18:17:34 +02:00
0854a5d234
litex_m2_baseboard: Add Ethernet/Etherbone support.
2021-09-16 18:02:55 +02:00
8d2f75ca6d
litex_m2_baseboard: Add PMODs connectors.
2021-09-16 17:48:53 +02:00
3ad0eb6992
Add initial LiteX M2 Baseboard support with Clk/Serial/Buttons.
2021-09-16 17:44:50 +02:00
67756e53ae
Merge pull request #269 from kammoh/readme_zybo_fpga
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Update README.md
2021-09-15 07:34:20 -07:00
b75af2f21c
Update README.md
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FPGA on "Zybo Z7" is a 7-Series Zynq not a Zynq Ultrascale+
2021-09-15 10:21:10 -04:00
078b1ed7b7
CONTRIBUTORS: Update.
2021-09-15 14:59:42 +02:00
26943959b5
Merge pull request #268 from trabucayre/runber_support
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Add runber support
2021-09-15 08:32:05 +02:00
1ca77d6921
Merge pull request #267 from trabucayre/tangnano4k_fix_period
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platforms/sipeed_tang_nano_4k: fix period computation
2021-09-15 08:28:19 +02:00
7ccae3332d
Add runber support
2021-09-15 06:50:57 +02:00
fed36afaba
platforms/sipeed_tang_nano_4k: fix period computation
2021-09-15 06:46:29 +02:00
68fb163a27
targets: Remove spiflash mapping on targets where it's no longer useful.
2021-09-14 18:35:13 +02:00
db91eda899
linsn_rv901t.py: Update Ethernet and add Etherbone support.
2021-09-13 19:35:05 +02:00
b9f2a4c483
Merge pull request #266 from teknoman117/mojov3
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Add Mojo V3 support
2021-09-10 14:01:59 +02:00
b8373a361d
alchitry_mojo: new board
2021-09-10 02:40:31 -07:00
d4613562a8
Merge pull request #265 from trabucayre/tangNano4K_connector
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platforms/sipeed_tang_nano_4k: add P6 and P7 connectors
2021-09-09 11:43:05 +02:00
cacb76450f
Merge pull request #264 from teknoman117/alchitry-au
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Add Alchitry Au as new board
2021-09-09 11:42:37 +02:00
3622661fa8
test/test_targets: Remove build directory before build.
2021-09-09 11:36:18 +02:00
945e48ea83
platforms/sipeed_tang_nano_4k: add P6 and P7 connectors
2021-09-09 11:35:14 +02:00
8d91489756
tang_nano_4k: Add more IOs.
2021-09-09 11:23:20 +02:00
9bbdb87130
alchitry_au: new board
2021-09-09 00:03:19 -07:00
88534c6689
tang_nano_4k: Fix typo in sipeed.
2021-09-08 23:02:39 +02:00
ce52c8c5ed
beaglewire: Fix typo in qwertyembedded.
2021-09-08 21:29:29 +02:00
ecebe7e267
Add initial SiSpeed Tang Nano 4K support (Led blink only for now...).
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./sispeed_tang_nano_4k.py --build --load
Build with Gowin EDA.
Load with OpenFPGALoader.
2021-09-08 19:36:46 +02:00
129b95f9b5
sqrl_acorn: Update pre_placement_commands with new XilinxVivadCommands.
2021-09-08 16:27:30 +02:00
7fa22a494b
arty: Switch SPI Flash rate to 1:2 (DDR) (Possible on Arty since SPI Flash's clk does not require use of STARTUPE2).
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On the Digilent Arty, the SPI Flash's clk is connected to CCLK (that can be driven
through the STARTUPE2) but also to another generic IO that can be use to drive the
clock through DDR primitives.
2021-09-07 15:07:59 +02:00
aa2209729f
gsd_butterstick: Force uart_name to crossover when set to serial.
2021-09-02 15:23:05 +02:00
fddca1cd40
gsd_butterstick: Add SDCard (SPI & SD modes) support.
2021-09-02 14:06:09 +02:00
596f430326
gsd_butterstick: Add SPI Flash support.
2021-09-02 11:28:21 +02:00
1bbbf5b3e7
gsd_butterstick: Add SYZYGY0/1 IOs to connectors.
2021-09-02 10:26:18 +02:00
55ea71bd01
gsd_butterstick: Add initial DDR3 support.
...
Validated with:
./gsd_butterstick.py --uart-name=crossover --with-etherbone --csr-csv=csr.csv --build --load
litex_server --udp
litex_term bridge
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2021 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Sep 1 2021 19:09:52
BIOS CRC passed (3d349845)
Migen git sha1: 27dbf03
LiteX git sha1: 315fbe18
--=============== SoC ==================--
CPU: VexRiscv @ 75MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128KiB
SRAM: 8KiB
L2: 8KiB
SDRAM: 524288KiB 16-bit @ 300MT/s (CL-6 CWL-5)
--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Read leveling:
m0, b00: |01110000| delays: 02+-01
m0, b01: |00000000| delays: -
m0, b02: |00000000| delays: -
m0, b03: |00000000| delays: -
best: m0, b00 delays: 02+-01
m1, b00: |01110000| delays: 02+-01
m1, b01: |00000000| delays: -
m1, b02: |00000000| delays: -
m1, b03: |00000000| delays: -
best: m1, b00 delays: 02+-01
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
Write: 0x40000000-0x40200000 2.0MiB
Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
Write speed: 13.6MiB/s
Read speed: 15.6MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex>
2021-09-01 19:21:16 +02:00
1f25a98476
butterstick: Add Ethernet/Etherbone support (UART crossover working over Etherbone).
2021-09-01 18:03:13 +02:00
1f149ece6b
Add intial ButterStick support (with just Clk, Buttons and Leds).
2021-09-01 17:33:54 +02:00
fb9bb17835
Merge pull request #259 from danc86/clnexevn-unreserve-spi-flash-pins
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lattice_crosslink_nx_evn: don't set MASTER_SPI_PORT=SERIAL
2021-09-01 12:18:41 +02:00
b3823d92b0
Add CONTRIBUTORS file.
2021-09-01 11:11:27 +02:00
Florent Kermarrec
alainlou
Tim Ansell
Kamyar Mohajerani
Gwenhael Goavec-Merou
Nathaniel R. Lewis