afbf9eb8c9
target/xxx: remove with-uartbone, add_uartbone and deal with case where uartbone is required inconditionnally
2023-10-23 17:43:13 +02:00
ce121663ff
targets/uartbone: Update with LiteX change.
2023-07-20 15:42:47 +02:00
f400179b5b
targets: Import all from litex.gen on all targets.
2023-02-23 09:09:33 +01:00
58489ebebf
targets/BaseSoC: Cleanup parameters.
2022-11-08 12:31:49 +01:00
9e7079c4c8
targets: Remove int() on BaseSoC's sys_clk_freq.
2022-11-08 11:54:17 +01:00
b0e6414519
targets: Cleanup arguments and switch --sys-clk-freq to float (avoid conversion in code).
2022-11-08 10:41:35 +01:00
16b9677acd
targets: Switch to soc_core_argdict.
...
The next move was to remove soc_core and only keep soc; so this is probably the right time to do
it in targets to avoid having to handle it later.
2022-11-07 08:43:26 +01:00
33b0400aed
targets: Update LiteXArgumentParser imports.
2022-11-06 21:39:52 +01:00
9960f38d95
targets: replace LiteXSoCArgumentParser by LiteXArgumentParser, remove tasks done LiteXArgumentParser
2022-11-06 11:27:47 +01:00
548a028730
targets: Switch to LiteXModule to simplify/cleanup code.
2022-10-27 21:21:37 +02:00
eadea43fa1
honours lattice toolchain args
2022-06-22 21:05:35 +02:00
45494f60e0
targets: Change SoC/Software headers generation behaviour (Now only generated with --build).
...
Re-generating the SoC/Software headers was causing some un-expected behaviours for users not familiar
with the flow. For example doing a --load with a different configuration, was re-generating the Software
headers and messing up things when trying to run software on the SoC.
2022-05-06 15:14:32 +02:00
a611f035d6
targets: Move CRG before SoCCore init (More logical and simplify some specific reset schemes) and switch SoCCore to one line when possible.
...
Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical.
Also do some minor updates/cosmetic changes while touching CRG/SoCCore.
2022-04-21 12:19:45 +02:00
00ff61baa9
targets: Simplify clock domains and remove useless reset_less.
...
rst was not directly assigned/used on reset_less clock domains, so reset_less
property was not really useful. With the changes on stream.CDC, having a rst
(Even fixed at 0) is now mandatory on clock domains involved in the CDC, so this
also fixes targets.
2022-04-01 11:30:38 +02:00
9d452b0d74
targets: Create target_group for target arguments.
2022-03-21 18:37:40 +01:00
cc8da9d341
targets: Simplify imports and switch to LiteXSocArgumentParser.
...
CPU parameters are now selectively exposed to the user:
./digilent_arty.py --cpu-type=vexriscv_smp --help will show VexRiscv-SMP parameters.
./digilent_arty.py --cpu-type=naxriscv --help will show NaxRiscv parameters.
2022-03-21 16:59:40 +01:00
5f2ccb2d32
targets: Switch from bridge to crossover.
2022-01-19 17:03:17 +01:00
fccb952c4b
target: Remove ident_version=True no longer required.
2022-01-18 17:13:02 +01:00
4b6a9b2cf0
targets/spiflash: Simplify self.cpu.set_reset_address call.
2022-01-07 15:19:23 +01:00
8151bf7ffa
targets: Update and simplify SPI-Flash support (Address is now automatically allocated).
2022-01-07 10:34:47 +01:00
53dc00eab7
targets/parser: Rely on argparse.ArgumentDefaultsHelpFormatter to provide default in help description.
...
Also do minor adjustments while doing this.
2022-01-05 17:06:40 +01:00
8664b59f23
targets: Fix --bios-flash-offset support and other minor cleanups.
2021-12-20 21:41:12 +01:00
8df797c716
lattice_ice40up5k_evn: Switch to LiteSPI.
2021-07-29 19:50:36 +02:00
55ba0591df
targets: Remove SpiFlash imports (Obsolete since integration is provided by LiteX).
2021-07-27 19:35:19 +02:00
1920db3535
Add with_led_chaser argument to constructor of boards using LedChaser submodule.
2021-07-06 16:39:37 -05:00
213d100860
Lattice iCE40 UltraPlus Breakout board (iCE40UP5K-B-EVN) added
2021-05-04 12:19:21 +02:00
Gwenhael Goavec-Merou
Florent Kermarrec
Gwenhael Goavec-Merou
Joey Bushagour
Fabien