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1,505 Commits 9 Branches 14 Tags 12 MiB
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16 Commits

Author SHA1 Message Date
Florent Kermarrec 877bc4b45e targets: Use full imports (vendor_board). 2022-05-02 12:55:11 +02:00
Florent Kermarrec a611f035d6 targets: Move CRG before SoCCore init (More logical and simplify some specific reset schemes) and switch SoCCore to one line when possible. 
Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical.
Also do some minor updates/cosmetic changes while touching CRG/SoCCore.
 2022-04-21 12:19:45 +02:00
Florent Kermarrec 00ff61baa9 targets: Simplify clock domains and remove useless reset_less. 
rst was not directly assigned/used on reset_less clock domains, so reset_less
property was not really useful. With the changes on stream.CDC, having a rst
(Even fixed at 0) is now mandatory on clock domains involved in the CDC, so this
also fixes targets.
 2022-04-01 11:30:38 +02:00
Florent Kermarrec 9d452b0d74 targets: Create target_group for target arguments. 2022-03-21 18:37:40 +01:00
Florent Kermarrec cc8da9d341 targets: Simplify imports and switch to LiteXSocArgumentParser. 
CPU parameters are now selectively exposed to the user:
./digilent_arty.py --cpu-type=vexriscv_smp --help will show VexRiscv-SMP parameters.
./digilent_arty.py --cpu-type=naxriscv --help will show NaxRiscv parameters.
 2022-03-21 16:59:40 +01:00
Florent Kermarrec 773444a7dd targets: Switch to get_bios_filename/get_bitstream_filename. 2022-03-17 09:21:05 +01:00
Florent Kermarrec 99a66274c8 xilinx_alveo_u280: Switch HBM2 to USPHBM2 now integrated in LiteX. 2022-03-03 16:11:48 +01:00
Sergiu Mosanu 7ed633dc4b add guideline for serial interface 2022-02-08 12:54:34 -05:00
Sergiu Mosanu 5a0f69502b enable use of HBM for linux boot 2022-02-08 12:18:38 -05:00
Florent Kermarrec fccb952c4b target: Remove ident_version=True no longer required. 2022-01-18 17:13:02 +01:00
Florent Kermarrec 53dc00eab7 targets/parser: Rely on argparse.ArgumentDefaultsHelpFormatter to provide default in help description. 
Also do minor adjustments while doing this.
 2022-01-05 17:06:40 +01:00
Sergiu Mosanu 99ff82c75a xilinx_alveo_u280: Add more IOs and enable HBM2. 2021-07-28 18:11:49 +02:00
Sergiu Mosanu 8ad91d9eb3 fix cmdltncy, with_led 2021-04-27 17:30:56 -04:00
Sergiu Mosanu 5519c931f8 xilinx_alveo_u280: Fix DDR4 (tested with 8 modules on C0 and C1). 2021-04-12 08:07:16 +02:00
Florent Kermarrec ba01776432 targets/add_sdram: Simplify call by removing useless arguments. 
- main_ram mem_map is now directly used by add_sdram when origin is None.
- max_sdram_size/min_l2_data_width are no longer exposed as targets arguments this can
still be used enforced directly in the few cases it is useful.
 2021-03-29 15:28:31 +02:00
Florent Kermarrec 8a3cacae32 boards: Add Vendor prefix to platforms/targets name when useful and when multiple boards from the same vendor. (With Retro-Compat on the imports). 2021-03-25 14:11:17 +01:00