4fbf2fc7de
targets: Replace self.add_wb_master with self.bus.add_master.
2022-04-21 15:32:19 +02:00
a611f035d6
targets: Move CRG before SoCCore init (More logical and simplify some specific reset schemes) and switch SoCCore to one line when possible.
...
Moving CRG simplify reset with NaxRiscv debug module and is in fact more logical.
Also do some minor updates/cosmetic changes while touching CRG/SoCCore.
2022-04-21 12:19:45 +02:00
c081177d77
pynq_z1/zybo_z7: Update .xci (With changes from #99 ).
2022-03-24 09:15:36 +01:00
9d452b0d74
targets: Create target_group for target arguments.
2022-03-21 18:37:40 +01:00
cc8da9d341
targets: Simplify imports and switch to LiteXSocArgumentParser.
...
CPU parameters are now selectively exposed to the user:
./digilent_arty.py --cpu-type=vexriscv_smp --help will show VexRiscv-SMP parameters.
./digilent_arty.py --cpu-type=naxriscv --help will show NaxRiscv parameters.
2022-03-21 16:59:40 +01:00
773444a7dd
targets: Switch to get_bios_filename/get_bitstream_filename.
2022-03-17 09:21:05 +01:00
fccb952c4b
target: Remove ident_version=True no longer required.
2022-01-18 17:13:02 +01:00
296c99f065
digilent_pynq_z1: Do minor cosmetic cleanups.
2022-01-14 09:39:42 +01:00
a3d168e4c0
HDMI Terminal Support
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Copyright notice update.
2022-01-13 23:28:43 +05:30
ed50c84e0d
Support for Digilent Pynq Z1
2022-01-11 19:33:12 +05:30
Florent Kermarrec
Rakesh Peter