Florent Kermarrec
|
39d979a9d3
|
targets/Ultrascale: add missing AsyncResetSynchronizer import.
|
2020-11-09 10:25:05 +01:00 |
|
Florent Kermarrec
|
2b17dc1b89
|
target: add rst signal to CRG to allow full reset of the SoC on reboot command.
|
2020-11-04 11:13:42 +01:00 |
|
Florent Kermarrec
|
814e7630e4
|
targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
|
2020-10-13 12:10:29 +02:00 |
|
Florent Kermarrec
|
06137452d2
|
targets/xcu1525: use ddram_channel to select clk300.
|
2020-10-13 11:57:00 +02:00 |
|
Florent Kermarrec
|
c3ea04b6e9
|
targets/s7/us: update sdram (manual cmd_latency no longer needed).
|
2020-10-12 18:46:21 +02:00 |
|
Florent Kermarrec
|
de09b10726
|
targets/xcu1525: add ddram-channel selection and rewrite DRC workaround comment.
|
2020-09-24 18:19:49 +02:00 |
|
Florent Kermarrec
|
77ba49f2bb
|
targets/pcie: update timing_constraints (now provided by the .xci).
|
2020-09-24 09:50:55 +02:00 |
|
Florent Kermarrec
|
ad48728160
|
xcu1525: update headers (were still using old format).
|
2020-09-04 19:59:09 +02:00 |
|
Florent Kermarrec
|
2eda9d0252
|
xcu1525: add DDR4 IOs for C1/C2/C3 and fix compilation (untested).
|
2020-09-04 11:34:33 +02:00 |
|
Florent Kermarrec
|
7b6b71d4e3
|
xcu1525: add initial DDR4 support in C0 (untested).
|
2020-09-03 19:48:23 +02:00 |
|
Florent Kermarrec
|
5a62a07b45
|
xcu1525: add initial PCIe support (untested).
|
2020-09-03 19:26:02 +02:00 |
|
Florent Kermarrec
|
51e881d1ff
|
add minimal xcu1525 support (VCU1525 or BCU1525 boards).
|
2020-09-03 19:06:43 +02:00 |