9d452b0d74
targets: Create target_group for target arguments.
2022-03-21 18:37:40 +01:00
cc8da9d341
targets: Simplify imports and switch to LiteXSocArgumentParser.
...
CPU parameters are now selectively exposed to the user:
./digilent_arty.py --cpu-type=vexriscv_smp --help will show VexRiscv-SMP parameters.
./digilent_arty.py --cpu-type=naxriscv --help will show NaxRiscv parameters.
2022-03-21 16:59:40 +01:00
773444a7dd
targets: Switch to get_bios_filename/get_bitstream_filename.
2022-03-17 09:21:05 +01:00
fccb952c4b
target: Remove ident_version=True no longer required.
2022-01-18 17:13:02 +01:00
53dc00eab7
targets/parser: Rely on argparse.ArgumentDefaultsHelpFormatter to provide default in help description.
...
Also do minor adjustments while doing this.
2022-01-05 17:06:40 +01:00
d6fc4b412e
efinix_trion_t120/t20_dev_kit: Switch back to 100MHz (now that timings constraints are correctly applied).
2021-11-12 07:58:51 +01:00
7ce8567d9b
targets/efinix: Bitstreams now directly generated to gateware directory.
2021-11-11 11:19:39 +01:00
c7a91f9eab
efinix: Enable identifier on SoC (issue fixed in LiteX).
2021-10-25 19:33:49 +02:00
4bcfde8882
efinix: Avoid no_we on ROM/RAMs (no longer required).
2021-10-25 19:10:03 +02:00
d13a8d54b8
efinix_trion_txy_dev_kit: Lower sys_clk_freq for now to 50MHz, enable QSPI on T120 BGA576 dev kit.
...
Now possible with recent LiteX changes to support Tristate IOs.
2021-10-25 18:35:35 +02:00
012c1d9705
efinix_trion_t20: Minor changes (move serial to platform, fix platform copyright).
2021-10-21 10:10:35 +02:00
1f65d37121
Enable writing to flash for T20
2021-10-15 16:44:35 +02:00
d9638c40b8
Initial support for Efinix Trion T20 BGA256 Dev Kit
2021-10-15 12:26:15 +02:00
Florent Kermarrec
Miodrag Milanovic