Florent Kermarrec
|
75f7120ff9
|
targets/Ultrascale: Fix build since idelay's reset is now handled by the PLL (with_reset=True).
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2021-03-11 10:00:06 +01:00 |
|
Florent Kermarrec
|
21207533b0
|
targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence).
|
2021-03-04 19:49:03 +01:00 |
|
Florent Kermarrec
|
d73bd2f7ce
|
targets/xilinx: add comment on sys_clk to pll.clkin false path.
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2021-01-07 08:01:54 +01:00 |
|
Florent Kermarrec
|
1ac1c6857f
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targets/xilinx: add false path constraint between sys_clk and pll.clkin.
The SoC reset added recently creates a path between sys_clk and pll.clkin
clock domains that is reported by the tools but that can be safely ignored.
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2021-01-07 00:02:46 +01:00 |
|
Florent Kermarrec
|
778ce53865
|
targets/xcu1525: add SATA.
|
2020-11-17 15:27:42 +01:00 |
|
Florent Kermarrec
|
d42af3ea19
|
targets: add --sys-clk-freq support to all targets.
|
2020-11-12 18:07:28 +01:00 |
|
Florent Kermarrec
|
843e724e3d
|
targets/pcie: simplify using new LiteX's add_pcie method and enable it on all devices supported by LitePCIe.
|
2020-11-12 16:39:42 +01:00 |
|
Florent Kermarrec
|
7a9f175450
|
targets/pcie: remove force of csr_data_width to 32 (this is now the default) but just add a check on the pcie block.
|
2020-11-12 12:08:20 +01:00 |
|
Florent Kermarrec
|
bd4e92ad13
|
targets: cleanup, uniformize build arguments between targets.
|
2020-11-12 11:46:00 +01:00 |
|
Florent Kermarrec
|
39d979a9d3
|
targets/Ultrascale: add missing AsyncResetSynchronizer import.
|
2020-11-09 10:25:05 +01:00 |
|
Florent Kermarrec
|
2b17dc1b89
|
target: add rst signal to CRG to allow full reset of the SoC on reboot command.
|
2020-11-04 11:13:42 +01:00 |
|
Florent Kermarrec
|
814e7630e4
|
targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
|
2020-10-13 12:10:29 +02:00 |
|
Florent Kermarrec
|
06137452d2
|
targets/xcu1525: use ddram_channel to select clk300.
|
2020-10-13 11:57:00 +02:00 |
|
Florent Kermarrec
|
c3ea04b6e9
|
targets/s7/us: update sdram (manual cmd_latency no longer needed).
|
2020-10-12 18:46:21 +02:00 |
|
Florent Kermarrec
|
de09b10726
|
targets/xcu1525: add ddram-channel selection and rewrite DRC workaround comment.
|
2020-09-24 18:19:49 +02:00 |
|
Florent Kermarrec
|
77ba49f2bb
|
targets/pcie: update timing_constraints (now provided by the .xci).
|
2020-09-24 09:50:55 +02:00 |
|
Florent Kermarrec
|
ad48728160
|
xcu1525: update headers (were still using old format).
|
2020-09-04 19:59:09 +02:00 |
|
Florent Kermarrec
|
2eda9d0252
|
xcu1525: add DDR4 IOs for C1/C2/C3 and fix compilation (untested).
|
2020-09-04 11:34:33 +02:00 |
|
Florent Kermarrec
|
7b6b71d4e3
|
xcu1525: add initial DDR4 support in C0 (untested).
|
2020-09-03 19:48:23 +02:00 |
|
Florent Kermarrec
|
5a62a07b45
|
xcu1525: add initial PCIe support (untested).
|
2020-09-03 19:26:02 +02:00 |
|
Florent Kermarrec
|
51e881d1ff
|
add minimal xcu1525 support (VCU1525 or BCU1525 boards).
|
2020-09-03 19:06:43 +02:00 |