Commit Graph

9 Commits

Author SHA1 Message Date
Florent Kermarrec 00ff61baa9 targets: Simplify clock domains and remove useless reset_less.
rst was not directly assigned/used on reset_less clock domains, so reset_less
property was not really useful. With the changes on stream.CDC, having a rst
(Even fixed at 0) is now mandatory on clock domains involved in the CDC, so this
also fixes targets.
2022-04-01 11:30:38 +02:00
Florent Kermarrec 9d452b0d74 targets: Create target_group for target arguments. 2022-03-21 18:37:40 +01:00
Florent Kermarrec cc8da9d341 targets: Simplify imports and switch to LiteXSocArgumentParser.
CPU parameters are now selectively exposed to the user:
./digilent_arty.py --cpu-type=vexriscv_smp --help will show VexRiscv-SMP parameters.
./digilent_arty.py --cpu-type=naxriscv --help will show NaxRiscv parameters.
2022-03-21 16:59:40 +01:00
Florent Kermarrec 773444a7dd targets: Switch to get_bios_filename/get_bitstream_filename. 2022-03-17 09:21:05 +01:00
Florent Kermarrec 1623ba5942 targets/stlv7325: Reduce sys_clk_freq to 100MHz.
See https://github.com/enjoy-digital/litedram/issues/285.
2022-02-25 09:04:07 +01:00
Florent Kermarrec 872113e1cc stlv7325: Add SDCard support. 2022-02-24 18:02:43 +01:00
Florent Kermarrec a08f346d90 stlv7325: Add Etherbone support (untested). 2022-02-24 17:43:53 +01:00
Florent Kermarrec b1550f006a stlv3225: Minor Review/Cleanup, switch to JTAG HS2 programmer. 2022-02-24 17:17:08 +01:00
Andrew Gillham 174d958ca7 Initial support for STLV7325 Kintex-7 board. 2022-02-23 18:28:55 +01:00