5be6a46cfe
README.md: Add sipeed_tang_mega_138k to supported boards.
2023-09-26 10:36:04 +02:00
c14d66cb6b
analog_pocket: Add Serial (to fix CI) and add to board list.
2023-09-21 10:11:55 +02:00
e9335cd67a
Fix pins in Alchitry Cu platform, add target for Alchitry Cu
2023-06-27 21:35:55 +05:30
3308b6ddf3
README.md: Update boards.
2023-03-22 10:53:02 +01:00
8a6f0bd94f
opalkelly_xem8320: Review and update to recent LiteX changes.
2023-03-01 09:16:51 +01:00
bd20b31a5c
add support for machdyne kopflos board
2023-02-21 11:18:22 +01:00
549905bc38
README: Bump year.
2023-02-16 09:08:38 +01:00
456548afab
README: Update boards list.
2023-02-16 09:07:50 +01:00
a0fd3e7536
Add initial OCP-TAP TimeCard support with PCIe/SPIFlash/Leds/Buttons/DNA/XADC (Compiles but untested).
2023-01-12 18:50:23 +01:00
f0dc9a6874
initial support for machdyne konfekt and noir
2022-12-30 17:00:35 +01:00
f1899954e9
Add initial NewAE CW305 board support.
2022-09-13 12:38:30 +02:00
fdd16b796f
README: Update boards list.
2022-08-24 15:26:34 +02:00
313e758ffe
Updated copywrite and renamed to avnet_aesku40
2022-06-03 20:49:52 -06:00
45494f60e0
targets: Change SoC/Software headers generation behaviour (Now only generated with --build).
...
Re-generating the SoC/Software headers was causing some un-expected behaviours for users not familiar
with the flow. For example doing a --load with a different configuration, was re-generating the Software
headers and messing up things when trying to run software on the SoC.
2022-05-06 15:14:32 +02:00
0ce7f8354c
Add initial LimeSDR Mini V2 support (With SoC + USB3 (FT245PHYSynchronous)).
...
python3 -m litex_boards.targets.limesdr_mini_v2 --csr-csv=csr.csv --build --load
litex_server --jtag --jtag-config=openocd_limesdr_mini_v2.cfg
litex_term crossover
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2022 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on May 3 2022 18:59:46
BIOS CRC passed (5f29afcc)
LiteX git sha1: a4cc859d
--=============== SoC ==================--
CPU: VexRiscv @ 80MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128KiB
SRAM: 8KiB
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex> ident
Ident: LiteX SoC on LimeSDR-Mini-V2 2022-05-03 18:59:29
2022-05-03 19:04:06 +02:00
14f4500653
README: Update boards list.
2022-04-21 10:39:54 +02:00
8c51cb12c8
Merge pull request #383 from sysmanalex/master
...
Added Kintex-7 xc7k420t xc7k420tiffg901-2L named as u420t board
2022-04-21 10:02:05 +02:00
5aab6f01b6
README: Update boards list.
2022-04-14 12:30:19 +02:00
1e00a43fdd
board u420t kintex update v0.2
2022-04-13 00:12:59 +03:00
b8b0aead28
Added basic support for Arduino MKR Vidor 4000
2022-03-21 18:54:29 -07:00
e5fd58f1af
README: Add adi_adrv2crr_fmc.
2022-03-07 09:26:24 +01:00
ddd040bc42
README: Switch to python3 -m litex_boards.targets.<board> and remove .py in boards list.
2022-03-01 14:08:34 +01:00
89a80e713e
README: Update boards picture with reduced jpg version.
2022-03-01 14:03:00 +01:00
1ce0a4b070
README: Update and simplify boards listing.
2022-03-01 11:57:32 +01:00
5a0f69502b
enable use of HBM for linux boot
2022-02-08 12:18:38 -05:00
d9303e096b
Bump year.
2022-01-05 09:09:16 +01:00
1b676f929a
cleanup and ease of use
...
- update README
- delete some unnecessary toolchain commands (copied from trenz boards)
- use minimal cpu_variant by default when vexriscv is selected
2021-10-03 13:21:45 -04:00
4a52996106
Wukong board improvements
...
This adds support for v2 of the board via a --board-version argument
and a way to select the FPGA speed grade via a --speed-grade argument.
Note that the speed grade now defaults to -1. QMTech confirmed that
V1 of the board were made in two batches, one with -1 and one with -2,
while V2 of the board is all -1. So -1 is the safer default.
This also fixes the inversion of j10 and j11 and a typo in the pin
definition of jp3
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2021-09-24 12:13:56 +10:00
610e82d774
Add initial RZ-EasyFPGA support! ( #270 )
2021-09-21 09:55:22 +02:00
b75af2f21c
Update README.md
...
FPGA on "Zybo Z7" is a 7-Series Zynq not a Zynq Ultrascale+
2021-09-15 10:21:10 -04:00
781d83bab6
Add support for EBAZ4205 'Development' Board
...
Usage:
```
./ebaz4205.py --cpu-type=vexriscv --build --load
```
```
$ pwd
litex-boards/litex_boards/targets
```
Tip: Use `GTKTerm` to connect to /dev/ttyUSB0 (usually) and interact
with the LiteX BIOS.
References:
- https://github.com/fusesoc/blinky#ebaz4205-development-board
- https://github.com/olofk/serv/#ebaz4205-development-board
- https://github.com/xjtuecho/EBAZ4205#ebaz4205
- https://github.com/nmigen/nmigen-boards/pull/180 (merged)
- https://github.com/olofk/corescore/pull/33
- The existing 'Zybo Z7' example
Note: The `PS7` stuff remains untested via LiteX for now.
2021-08-31 18:54:49 +02:00
126c98488a
update IRC channel
2021-08-16 14:18:08 -04:00
25867c4dcb
Merge pull request #218 from helium729/master
...
Add digilent basys3 board support
2021-05-23 19:46:58 +02:00
dd5a4bdc92
CYC1000: Add initial support of CYC1000 board
2021-05-22 21:17:27 +02:00
95b589fc22
add info to README
2021-05-17 16:49:04 +08:00
5ae130661f
Merge pull request #213 from hansfbaier/icesugar
...
muselab_icesugar: first basic version which boots
2021-05-07 08:50:50 +02:00
c2e0f6026e
muselab_icesugar: first basic version that boots
2021-05-07 11:50:28 +07:00
eec1078736
add QMTECH XC7A35T core board + daughter board
2021-05-06 05:50:48 +07:00
9e42183066
update AU280 description
2021-04-27 17:29:55 -04:00
f4ea3fb0d9
Merge pull request #168 from hplp/alveo_u280
...
Alveo U280 board
2021-03-10 11:16:32 +01:00
767e2875b3
README.md: fix typo
2021-02-26 04:55:11 +07:00
6f558a5d65
Add board support for Terasic/Arrow DECA board
2021-02-25 12:25:43 +07:00
bc255a6a0d
arrow_sockit: Add README table entry and test target
2021-02-25 12:25:43 +07:00
5a1447dc5c
mention HBM2
2021-01-15 17:52:17 -05:00
58e25757eb
list Alveo U280
2021-01-15 12:16:10 -05:00
e1f9fd1a25
README: update and center banner.
2020-12-17 18:55:13 +01:00
b9d9af3183
ci: switch from Travis CI to Github Actions.
2020-11-24 14:01:23 +01:00
389b623fe2
targets/litefury: new target
...
LiteFury is an Artix-7 development board in the M.2 form factor
for PCIe accelerator development. It's similar to the Aller but
with an xc7a100t rather than an xc7a200t and no TPM module.
https://rhsresearch.com/collections/rhs-public/products/litefury
2020-11-19 21:52:14 -08:00
27f60b2e93
add initial Siglent SDS1104X-E support (Ethernet & DDR3 validated).
...
Pinout from https://github.com/360nosc0pe project.
2020-11-13 12:20:15 +01:00
f0581815f5
README: fix typo.
2020-07-28 17:44:30 +02:00
Florent Kermarrec
Mark1626
inc
AEW2015
Alex Petrov
John Simons
Sergiu Mosanu
alainlou
Benjamin Herrenschmidt
Kamyar Mohajerani
Dhiru Kholia
Jakub Cabal
helium729
Hans Baier
Nathaniel R. Lewis