a410e447e1
targets/kc705/sata: enable write support.
2020-10-30 14:51:40 +01:00
d626861e95
platforms/acorn_cle_215: add serial_io (on P2).
2020-10-29 12:10:12 +01:00
f9252fdd45
targets/kc705: simplify SATA using LiteX's add_sata integration method.
2020-10-29 10:16:40 +01:00
7da8628fba
targets/kc705: switch SATA to gen2.
2020-10-28 19:09:30 +01:00
931f6667ac
targets/kc705: add initial SATA support.
2020-10-26 15:15:24 +01:00
51934567fe
Merge pull request #118 from daveshah1/lifcl-vip
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Add CrossLink-NX VIP board platform and target
2020-10-22 11:03:47 +02:00
a38c1e7062
mist: add copyrights.
2020-10-22 10:48:58 +02:00
20720693c4
crosslink_nx_vip: Add HyperRAM support
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Signed-off-by: David Shah <dave@ds0.me>
2020-10-22 09:15:40 +01:00
b278d8bccc
Add CrossLink-NX VIP board platform and target
2020-10-22 09:15:35 +01:00
4541c39e94
Initial support for the MIST board ( https://github.com/mist-devel/mist-board/wiki )
2020-10-17 12:28:22 +02:00
814e7630e4
targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
2020-10-13 12:10:29 +02:00
06137452d2
targets/xcu1525: use ddram_channel to select clk300.
2020-10-13 11:57:00 +02:00
982cfd5ad5
platforms/xcu1525: fix ddram constraints, add clk300 constraints for all channels.
2020-10-13 11:50:36 +02:00
c3ea04b6e9
targets/s7/us: update sdram (manual cmd_latency no longer needed).
2020-10-12 18:46:21 +02:00
ddf7038c78
ulx3s: add 1.7 and 2.0 revisions support.
2020-10-12 13:23:26 +02:00
204d22c62b
Merge pull request #115 from BryanJacobs/master
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platforms/ulx3s: Update ULX3S SD pins for revision 2.0
2020-10-12 12:55:17 +02:00
3b11e60fb1
Update ULX3S SD pins for revision 2.0
2020-10-11 14:17:48 +11:00
5e67853a21
versa_ecp5: Add --eth-phy to select ethernet phy
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This also simplifies the logic a bit.
2020-10-09 23:56:16 +02:00
477734ff06
versa_ecp5: Add etherbone support
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Etherbone can be enabled with --with-etherbone
2020-10-09 00:53:08 +02:00
55da8b867a
platforms/zedboard: minor cleanups to uniformize with other platforms.
2020-10-07 11:25:20 +02:00
e225cbd28f
add zedboard platform to CI
2020-10-06 11:35:03 -07:00
8ee20a3f30
clean up imports
2020-10-06 11:24:34 -07:00
865c2bd98c
zedboard platform: clean up
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* remove unused code
* remove oled integration code
* openocd = default programmer
2020-10-06 11:00:36 -07:00
94ef096e77
Merge branch 'master' of https://github.com/litex-hub/litex-boards into HEAD
2020-10-06 10:05:34 -07:00
fff20f7532
targets/fomu: base it on iCEBreaker target + USB-ACM.
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This uniformizes Fomu target with others, provide a simple example of LiteX SoC
on Fomu and will ease maintenance.
2020-10-06 11:39:30 +02:00
12aed44577
add zedboard platform
2020-10-06 00:28:54 -07:00
79ef091a06
Merge pull request #110 from pepijndevos/gowin
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Add initial support for Trenz TEC0117 board
2020-10-05 19:50:09 +02:00
2ee32f2a15
Merge pull request #109 from geertu/orangecrab-Fix-r0.1-user_led-mapping
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orangecrab: Fix r0.1 user_led mapping
2020-10-02 09:40:41 +02:00
062fbd6c63
Merge pull request #108 from daveshah1/dave/nx-evn-doc
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crosslink_nx_evn: Improve documentation on UART jumpers
2020-10-02 09:40:04 +02:00
18e5def9f2
don't verify erase, very slow
2020-10-01 08:41:16 +02:00
81e4f1f158
add initial support for Trenz TEC0117 board
2020-09-30 14:01:36 +02:00
b2e34f5faf
orangecrab: Fix r0.1 user_led mapping
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On r0.1, all three user_leds are mapped to the same pin.
Fix this by mapping them to the pins connected to the individual
channels of the RGB LED, to match the comments, the schematics, and the
spirit of r0.2.
Untested on real hardware (I have r0.2 only).
Fixes: c94cbae0c0
2020-09-25 10:33:21 +02:00
de09b10726
targets/xcu1525: add ddram-channel selection and rewrite DRC workaround comment.
2020-09-24 18:19:49 +02:00
cc53206aff
targets/kcu105: create specific cd_eth for ethphy.
2020-09-24 10:25:55 +02:00
5b7288cfee
targets/kcu105: add Etherbone support.
2020-09-24 09:55:11 +02:00
77ba49f2bb
targets/pcie: update timing_constraints (now provided by the .xci).
2020-09-24 09:50:55 +02:00
c6610b4a3f
platforms/xcu1525: update ddram1/2/3 pinout.
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Using https://github.com/d953i/Custom_Part_Data_Files/blob/master/Boards/Xilinx_BCU1525/BCU1525_DIMMx.xdc
2020-09-20 21:07:00 +02:00
e5a144e9cd
platforms/xcu1525: update ddram0 pinout.
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Using https://github.com/d953i/Custom_Part_Data_Files/blob/master/Boards/Xilinx_BCU1525/BCU1525_DIMM0.xdc .
2020-09-19 23:28:34 +02:00
8ffb86c0dc
platforms/fk33/xcu1525: define pcie_x2/x4/x8/x16.
2020-09-19 22:37:05 +02:00
e4cdbe0f7a
targets/ac701: reduce ddram pads to the first 4 modules.
2020-09-05 11:46:07 +02:00
8a9fd02768
crosslink_nx_evn: Improve documentation on UART jumpers
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Signed-off-by: David Shah <dave@ds0.me>
2020-09-05 09:58:28 +01:00
76ac4a69a8
rename forest_kitten_33 platform/target to fk33.
2020-09-04 20:05:18 +02:00
979fee7517
forest_kitten_33: add pcie.
2020-09-04 20:02:43 +02:00
ad48728160
xcu1525: update headers (were still using old format).
2020-09-04 19:59:09 +02:00
ad4c483c32
Merge pull request #106 from daveshah1/dave/alveo_u250_pcie
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alveo_u250: Add PCIe x4 support
2020-09-04 19:22:48 +02:00
a68c00e48e
Merge pull request #104 from DerFetzer/colorlight_5a_75e_v6_0
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Add support for 5A-75E V6.0 board
2020-09-04 19:21:02 +02:00
ae6a052e57
alveo_u250: Add PCIe x4 support
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Based on the implementation in xcu1525
Signed-off-by: David Shah <dave@ds0.me>
2020-09-04 14:20:04 +01:00
2eda9d0252
xcu1525: add DDR4 IOs for C1/C2/C3 and fix compilation (untested).
2020-09-04 11:34:33 +02:00
7b6b71d4e3
xcu1525: add initial DDR4 support in C0 (untested).
2020-09-03 19:48:23 +02:00
5a62a07b45
xcu1525: add initial PCIe support (untested).
2020-09-03 19:26:02 +02:00
Florent Kermarrec
David Shah
YanekJ
Bryan Jacobs
Konrad Beckmann
Michael Betz
Pepijn de Vos
Geert Uytterhoeven