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33 Commits

Author SHA1 Message Date
Gwenhael Goavec-Merou 3050716e8e boards: digilent_nexys4ddr, kosagi_netv2, sipeed_tang_primer_20k: added eth_ip/remote_ip arg 2024-09-13 15:40:12 +02:00
Pepijn de Vos 8f59ebeffb WIP: make boards Gowin boards work with Apicula 2024-09-04 08:33:06 +02:00
Florent Kermarrec 347b477b07 sipeed_tang_primer_20k: Fix DDR3 module, SoC reset and remove DDR3 debug code. 
Now passing memtest with valid reported memory size:

       __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2023 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS CRC passed (d32a9529)

 LiteX git sha1: 85dadb82

--=============== SoC ==================--
CPU:		VexRiscv SMP-LINUX @ 48MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		64.0KiB
SRAM:		6.0KiB
L2:		512B
SDRAM:		128.0MiB 16-bit @ 192MT/s (CL-6 CWL-5)
MAIN-RAM:	128.0MiB

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Read leveling:
  m0, b00: |00000000| delays: -
  m0, b01: |00000000| delays: -
  m0, b02: |01100000| delays: 01+-00
  m0, b03: |00000000| delays: -
  best: m0, b02 delays: 01+-00
  m1, b00: |00000000| delays: -
  m1, b01: |00000000| delays: -
  m1, b02: |01100000| delays: 01+-00
  m1, b03: |00000000| delays: -
  best: m1, b02 delays: 01+-00
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB
   Read: 0x40000000-0x40200000 2.0MiB
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
  Write speed: 11.7MiB/s
   Read speed: 17.4MiB/s
 2023-08-29 16:50:17 +02:00
Florent Kermarrec c1088befe5 targets/CRG: Add rst signal when missing. 
Allow properly reseting the PLL from the SoC.
 2023-07-26 16:56:27 +02:00
Florent Kermarrec c9a0f5f50b targets/sipeed_tang_primer_20: Ethernet/Etherbone working. 
Test:
./sipeed_tang_primer_20k.py --cpu-type=serv --with-etherbone --build --load

ping 192.168.1.50
 2023-03-02 12:02:58 +01:00
Florent Kermarrec 4a724d9d2d targets/sipeed_tang_primer_20k/hdmi: Remove pn_swap on data lines that is no longer required. 2023-03-02 11:44:14 +01:00
Florent Kermarrec 9e73ba53ea platforms/sipeed_tang_primer_20k: Update hdmi pins to official dock version and fix compilation. 
Test:
./sipeed_tang_primer_20k.py --cpu-type=serv --with-video-terminal --build --load

Working.
 2023-03-02 11:39:41 +01:00
Florent Kermarrec f400179b5b targets: Import all from litex.gen on all targets. 2023-02-23 09:09:33 +01:00
Florent Kermarrec 9e7079c4c8 targets: Remove int() on BaseSoC's sys_clk_freq. 2022-11-08 11:54:17 +01:00
Florent Kermarrec b0e6414519 targets: Cleanup arguments and switch --sys-clk-freq to float (avoid conversion in code). 2022-11-08 10:41:35 +01:00
Florent Kermarrec 16b9677acd targets: Switch to soc_core_argdict. 
The next move was to remove soc_core and only keep soc; so this is probably the right time to do
it in targets to avoid having to handle it later.
 2022-11-07 08:43:26 +01:00
Florent Kermarrec 33b0400aed targets: Update LiteXArgumentParser imports. 2022-11-06 21:39:52 +01:00
Gwenhael Goavec-Merou 9960f38d95 targets: replace LiteXSoCArgumentParser by LiteXArgumentParser, remove tasks done LiteXArgumentParser 2022-11-06 11:27:47 +01:00
Florent Kermarrec 548a028730 targets: Switch to LiteXModule to simplify/cleanup code. 2022-10-27 21:21:37 +02:00
Florent Kermarrec 756e4f73fc sipeed_tang_primer_20k: Cleanup CRG. 2022-09-08 17:27:41 +02:00
Florent Kermarrec fadc5619f1 sipeed_tang_primer_20k/ddr3: Add litescope debug. 2022-09-07 17:46:46 +02:00
Florent Kermarrec 6c7157f799 sipeed_tang_primer_20k: Disable L2 cache to ease debug and add WIP status. 2022-09-07 17:07:07 +02:00
Florent Kermarrec d39d87b701 sipeed_tang_primer_20k: Switch to PHYPadsReducer and enable the 2 modules. 2022-09-07 12:06:22 +02:00
Icenowy Zheng 1663ded641 sipeed_tang_primer_20k: Add initial DDR3 integration (WIP). 2022-09-07 11:53:24 +02:00
Florent Kermarrec c9b8579ea3 sipeed_tang_primer_20k: Drive hdmi hdp to 1. 2022-09-07 11:22:02 +02:00
Florent Kermarrec abd20f560b sipeed_tang_primer: Minor cleanups (Rename standard dock to standard, reduce margin on hdmi5x). 2022-09-07 10:56:17 +02:00
Gwenhael Goavec-Merou ce5977bc1a targets/sipeed_tang_primer_20k: fix CLKDIV (disable reset and calibration) 2022-08-31 13:32:23 +02:00
Gwenhael Goavec-Merou 0c14bbf0dc sipeed_tang_primer_20k: adding dock lite support 2022-08-26 08:43:57 +02:00
Florent Kermarrec f2cb211432 sipeed_tang_primer_20k: Add buttons and prepare RGB Led. 
Synthesis issue with WS2812/GowinEDA for now.
 2022-08-04 16:32:50 +02:00
Florent Kermarrec 09b0c975f3 sipeed_tang_primer_20k: Add Ethernet/Etherbone (compiles but not yet working). 2022-07-26 12:53:42 +02:00
Florent Kermarrec abe08a96aa sipeed_tang_primer_20k: Add Video (Colorbars), compiles but does not seems to be working. 2022-07-26 12:25:10 +02:00
Florent Kermarrec 12b8063941 sipeed_tang_primer_20k: Add LedChaser through 204 pin SODIMM connector/Dock. 2022-07-26 11:44:03 +02:00
Florent Kermarrec 99c1e52664 targets/sipeed_tang_primier_20k: Add SPI Flash support (X1). 2022-07-26 10:35:44 +02:00
Florent Kermarrec 6677c1d0bd sipeed_tang_primer_20k: Enable SDCard (SPI and SD modes). 2022-07-26 10:27:19 +02:00
Florent Kermarrec 190f272c14 targets/sipeed_tang_primer_20k: Update build. 2022-06-29 10:00:47 +02:00
Florent Kermarrec ddc6140e25 sipeed_tang_primer_20k: Swithc to GW2APLL. 2022-06-03 12:01:49 +02:00
Florent Kermarrec 6e33d9249f sipeed_tang_primer_20k: Cleanup/Fix. 2022-06-03 11:40:10 +02:00
Icenowy Zheng b97d9cd9e8 sipeed_tang_primer_20k: new board 
Only initial support is added.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
 2022-06-03 00:24:20 +08:00