Florent Kermarrec
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1655cbf62f
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alinx_axau15: Add manual loc constraints on PCIe GTHE4 channels to avoid Vivado to remap them.
Board now correctly seen with lspci.
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2024-03-26 14:12:26 +01:00 |
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Florent Kermarrec
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cc7f092520
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alinx_axau15: Fix PCIe support compilation (still needs proper instance name).
Not yet working on hardware.
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2024-03-25 19:11:33 +01:00 |
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Florent Kermarrec
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191a5bb17a
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alinx_axau15: Add RGMII Ethernet/Etherbone support.
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2024-03-25 16:08:38 +01:00 |
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Florent Kermarrec
|
f50ee97520
|
alinx_axau15: Minor adjustments.
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2024-03-14 15:13:59 +01:00 |
John Simons
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721fa0b4b3
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axau15: added more FMC+ pins and made some corrrections
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2024-01-27 03:27:48 +01:00 |
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Florent Kermarrec
|
982038508e
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alinx_axau15/PCIe: Switch to Gen3/128-bit for now (configuration used on others Ultrascale+ Gen3 X4 boards).
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2023-12-28 19:56:52 +01:00 |
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Florent Kermarrec
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e229d1a0b6
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alinx_axau15: First review/cleanup pass and fix missing INTERNAL_VREF on bank 66.
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2023-12-28 19:48:50 +01:00 |
|
John Simons
|
2c2b3e318a
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Fixed pinout and first steps adding PCIe support
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2023-12-12 15:44:51 +01:00 |
|
John Simons
|
ab60d91138
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alinx_axau15: Fixed minor clock and sdcard reference issues
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2023-12-05 21:14:57 +01:00 |
|
John Simons
|
7be052911b
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alinx_axau15: Added new Alinx Artix US+ board
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2023-12-05 20:45:57 +01:00 |