0ee62dd681
add etherbone ip address option for relevant boards
2021-01-08 18:44:31 +01:00
d73bd2f7ce
targets/xilinx: add comment on sys_clk to pll.clkin false path.
2021-01-07 08:01:54 +01:00
1ac1c6857f
targets/xilinx: add false path constraint between sys_clk and pll.clkin.
...
The SoC reset added recently creates a path between sys_clk and pll.clkin
clock domains that is reported by the tools but that can be safely ignored.
2021-01-07 00:02:46 +01:00
06cb49af37
targets/arty: add variant support through --variant args.
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./arty.py --variant=a7-35 or a7-100
./arty_s7.py --variant=s7-50 or s7-25
2020-12-29 18:43:14 +01:00
18337cdf25
targets/arty: sync with litex repository
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Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
2020-12-07 17:32:40 +01:00
d42af3ea19
targets: add --sys-clk-freq support to all targets.
2020-11-12 18:07:28 +01:00
bd4e92ad13
targets: cleanup, uniformize build arguments between targets.
2020-11-12 11:46:00 +01:00
2b17dc1b89
target: add rst signal to CRG to allow full reset of the SoC on reboot command.
2020-11-04 11:13:42 +01:00
814e7630e4
targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
2020-10-13 12:10:29 +02:00
1781be166a
general: add SPDX License identifier to header and specify files are part of LiteX-Boards.
2020-08-23 15:00:17 +02:00
869ceadacb
targets: use platform.request_all on LedChaser.
2020-08-06 20:04:03 +02:00
760b8ff93a
arty: improve xy_pmod_io genericity (allow selecting the PMOD) and enable SDCard.
2020-07-24 16:29:35 +02:00
7b1bf9d74a
targets: remove sdcard specific clock domain (now generated by the PHY).
2020-07-03 20:09:30 +02:00
31e6997e70
sdcard: rename cd_sdcard to cd_sd to avoid unnecessary clock domain.
2020-07-01 12:58:48 +02:00
7a48a61605
targets: add indentifier on all targets.
2020-06-30 18:11:04 +02:00
efe33c9764
targets/arty: add fixed sdcard clock and remove sys2x (use NETWORKING interface_type on DDR3).
2020-06-25 11:21:24 +02:00
76df4e39c8
targets: simplify Ethernet/Etherbone integration on targets with both.
2020-05-29 19:20:27 +02:00
eeba64d7b2
targets: use soc.build_name in load/flash bitstream.
2020-05-21 09:12:29 +02:00
6f22f082ff
targets: add LedChaser on platforms with user_leds.
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Default to Chaser mode and similar user interface than GPIOOut.
2020-05-08 22:16:13 +02:00
2d9543b65e
targets: add build/load parameters on all targets.
2020-05-05 15:11:47 +02:00
6c31933e89
targets: switch to add_etherbone method.
2020-03-21 21:40:45 +01:00
3fb3ba18e8
targets: switch to add_ethernet method instead of EthernetSoC.
2020-03-21 18:29:52 +01:00
83e6fb29f8
targets: switch to SoCCore/add_sdram instead of SoCSDRAM.
2020-03-21 12:43:39 +01:00
fb1cab857a
targets/arty: use new ISERDESE2 MEMORY mode.
2020-03-20 18:59:17 +01:00
d8de4fbdfb
platforms/targets: keep in sync with LiteX
2020-02-27 11:06:53 +01:00
4edf196911
targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)
2020-02-11 17:45:35 +01:00
8211aca2e8
Avoid Official/Partner/Community differentiation: use same directory for all platforms/targets.
...
We initially wanted to provide different level of support for the platforms/targets, mainly
to avoid too much maintenance and let each contributor update its contributed platforms and
targets, but it's easier to update all platforms/targets all-together when LiteX evolves or
changes (and that's what has been done on litex-boards since the creation of the repository).
So let just simplify things and avoid this differentiation.
2020-02-03 09:36:30 +01:00
Hans Baier
Florent Kermarrec
Robert Winkler