Florent Kermarrec
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f661ee0ec9
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targets: fix import
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2019-08-26 11:00:12 +02:00 |
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Florent Kermarrec
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ac58d57a83
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targets: import platforms from litex_boards.platforms
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2019-08-26 09:09:40 +02:00 |
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Florent Kermarrec
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b84308cb58
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list all platforms/targets in platforms.py, targets.py to ease import
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2019-08-26 09:07:07 +02:00 |
Arnaud Durand
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618f41bb1e
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Update ecp5_evn.py
The system clock was driven directly while it should be driven by the PLL.
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2019-08-22 02:27:50 +02:00 |
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DurandA
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1abca7dcff
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Turn litex_boards.community into module
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2019-08-12 00:17:26 +02:00 |
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enjoy-digital
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ad21f15782
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Merge pull request #10 from DurandA/ecp5-evn
Add ECP5 Evaluation Board
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2019-08-09 12:37:36 +02:00 |
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DurandA
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c90950e319
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Default to 60 Mhz system clock on ECP5 Evaluation Board
Exact PLL clock can be derived from U1 12 Mhz or X5 50 Mhz clock.
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2019-08-09 11:58:30 +02:00 |
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DurandA
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9e6dccc277
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Remove ECP5 Evaluation Board programmer
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2019-08-09 11:54:49 +02:00 |
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DurandA
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4126ed21d5
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Add X5 clock and PLL to ECP5 Evaluation Board
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2019-08-09 11:54:38 +02:00 |
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DurandA
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c7444fe19c
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Add ECP5 Evaluation Board
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2019-08-09 09:45:13 +02:00 |
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Florent Kermarrec
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9f3ed82097
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keep up to date with LiteX
- use 1e9/freq for default_clk_period
- add default serial on tinyfpga_bx
- use S6PLL on minispartan6
- add SPIFlash pins on versa_ecp5
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2019-08-07 08:47:08 +02:00 |
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Florent Kermarrec
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a88970a67f
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move trellis board from community to partner
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2019-07-12 19:23:21 +02:00 |
David Shah
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a07e88d761
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community: Add TrellisBoard
Signed-off-by: David Shah <dave@ds0.me>
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2019-07-09 15:52:28 +01:00 |
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Florent Kermarrec
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aeddb93729
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add copyright header to all files, udpate.
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2019-06-24 12:13:54 +02:00 |
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Florent Kermarrec
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44d01edab9
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dispatch platforms/targets by level of support
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2019-06-10 18:59:49 +02:00 |
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Florent Kermarrec
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4213c75e48
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init repo with litex official boards
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2019-06-10 17:11:36 +02:00 |