Commit Graph

13 Commits

Author SHA1 Message Date
Florent Kermarrec e4a15f6064 targets/alinx_axau15: Remove unwanted add_sdcard() call. 2024-04-23 11:40:01 +02:00
Florent Kermarrec aaab2dcfe2 alinx_axau15: Add PCIe speed support (Gen3 or Gen4) and add SDCard parameter. 2024-04-19 14:35:13 +02:00
Florent Kermarrec 934002e7e6 targets/alinx_axau15: Avoid USPHBMPCIEPHY workaround. 2024-04-02 12:46:11 +02:00
Florent Kermarrec 1655cbf62f alinx_axau15: Add manual loc constraints on PCIe GTHE4 channels to avoid Vivado to remap them.
Board now correctly seen with lspci.
2024-03-26 14:12:26 +01:00
Florent Kermarrec cc7f092520 alinx_axau15: Fix PCIe support compilation (still needs proper instance name).
Not yet working on hardware.
2024-03-25 19:11:33 +01:00
Florent Kermarrec 191a5bb17a alinx_axau15: Add RGMII Ethernet/Etherbone support. 2024-03-25 16:08:38 +01:00
Florent Kermarrec f50ee97520 alinx_axau15: Minor adjustments. 2024-03-14 15:13:59 +01:00
John Simons 721fa0b4b3 axau15: added more FMC+ pins and made some corrrections 2024-01-27 03:27:48 +01:00
Florent Kermarrec 982038508e alinx_axau15/PCIe: Switch to Gen3/128-bit for now (configuration used on others Ultrascale+ Gen3 X4 boards). 2023-12-28 19:56:52 +01:00
Florent Kermarrec e229d1a0b6 alinx_axau15: First review/cleanup pass and fix missing INTERNAL_VREF on bank 66. 2023-12-28 19:48:50 +01:00
John Simons 2c2b3e318a Fixed pinout and first steps adding PCIe support 2023-12-12 15:44:51 +01:00
John Simons ab60d91138 alinx_axau15: Fixed minor clock and sdcard reference issues 2023-12-05 21:14:57 +01:00
John Simons 7be052911b alinx_axau15: Added new Alinx Artix US+ board 2023-12-05 20:45:57 +01:00