Gwenhael Goavec-Merou 938bf8b3a6 targets/lattice_certuspro_nx_xx,targets/lattice_crosslink_nx_xxx: pass platform to NXOSCA CTOR		2024-07-22 15:18:27 +02:00
..
platforms	plaforms/lattice_certuspro_nx_xx: SPI_MASTER_PORT disabled (required to have access to the flash), added default clk period constraints	2024-07-22 14:49:03 +02:00
prog	xilinx_zc706: new Xilinx/AMD Zynq7000 based board	2024-03-26 20:49:54 +01:00
targets	targets/lattice_certuspro_nx_xx,targets/lattice_crosslink_nx_xxx: pass platform to NXOSCA CTOR	2024-07-22 15:18:27 +02:00
__init__.py	litex_boards: Remove short imports since not really longer useful and mess up Python imports.	2022-05-03 17:53:57 +02:00