| .. |
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__init__.py
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…
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adi_adrv2crr_fmc.py
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di_adrv2crr_fmc: Bump PCIe to 8 lanes
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2024-02-05 11:43:02 +01:00 |
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adi_plutosdr.py
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…
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alchitry_au.py
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…
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alchitry_cu.py
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targets: Switch to LiteX byte size definitions.
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2024-06-13 10:04:19 +02:00 |
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alchitry_mojo.py
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…
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alientek_davincipro.py
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add Alientek DaVinci Pro FPGA board
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2024-04-22 14:44:53 +07:00 |
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aliexpress_xc7k70t.py
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aliexpress_xc7k70t: Review/Cleanup.
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2023-11-09 08:26:06 +01:00 |
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aliexpress_xc7k420t.py
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…
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alinx_ax7010.py
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…
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alinx_axau15.py
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targets/alinx_axau15: Remove unwanted add_sdcard() call.
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2024-04-23 11:40:01 +02:00 |
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alinx_axu2cga.py
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targets/alinx_axu2cga,xilinx_zcu216,xilinx_kv260: remove csr definition and GP0 connection to the SoC: now handled by znqmp core CPU
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2024-06-19 07:54:50 +02:00 |
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analog_pocket.py
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target/analog_pocket: Remove debug (Will be investigated externally).
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2023-10-27 15:32:36 +02:00 |
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antmicro_artix_dc_scm.py
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…
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antmicro_datacenter_ddr4_test_board.py
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target/xxx: remove with-uartbone, add_uartbone and deal with case where uartbone is required inconditionnally
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2023-10-23 17:43:13 +02:00 |
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antmicro_lpddr4_test_board.py
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target/xxx: remove with-uartbone, add_uartbone and deal with case where uartbone is required inconditionnally
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2023-10-23 17:43:13 +02:00 |
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antmicro_sdi_mipi_video_converter.py
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targets: Switch to LiteX byte size definitions.
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2024-06-13 10:04:19 +02:00 |
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arduino_mkrvidor4000.py
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…
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avnet_aesku40.py
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…
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berkeleylab_marble.py
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…
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camlink_4k.py
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…
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colognechip_gatemate_evb.py
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adding colognechip_gatemate_evb
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2024-02-28 17:27:21 +01:00 |
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colorlight_5a_75x.py
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target/xxx: remove with-uartbone, add_uartbone and deal with case where uartbone is required inconditionnally
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2023-10-23 17:43:13 +02:00 |
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colorlight_i5.py
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…
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colorlight_i9plus.py
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colorlight_i9plus: Switch to OpenFPGALoader for loading bitstreams.
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2024-04-02 08:44:25 +02:00 |
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decklink_intensity_pro_4k.py
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…
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decklink_mini_4k.py
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…
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decklink_quad_hdmi_recorder.py
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…
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digilent_arty.py
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#570: Update CAN support with LiteX https://github.com/enjoy-digital/litex/pull/2007.
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2024-07-05 10:26:28 +02:00 |
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digilent_arty_s7.py
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…
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digilent_arty_z7.py
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targets: All boards based on Zynq7000: remove csr definition and GP0 connection to the SoC: now handled by zynq700 core CPU
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2024-06-19 07:59:24 +02:00 |
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digilent_atlys.py
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…
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digilent_basys3.py
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…
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digilent_cmod_a7.py
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targets: Switch to LiteX byte size definitions.
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2024-06-13 10:04:19 +02:00 |
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digilent_genesys2.py
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#570: Update CAN support with LiteX https://github.com/enjoy-digital/litex/pull/2007.
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2024-07-05 10:26:28 +02:00 |
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digilent_nexys4.py
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…
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digilent_nexys4ddr.py
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…
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digilent_nexys_video.py
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targets/digilent_nexys_video: Use reset_buf on sys_clk's create_clkout to improve timings and demonstrate use.
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2023-11-07 13:22:30 +01:00 |
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digilent_pynq_z1.py
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targets: All boards based on Zynq7000: remove csr definition and GP0 connection to the SoC: now handled by zynq700 core CPU
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2024-06-19 07:59:24 +02:00 |
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digilent_zedboard.py
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targets: All boards based on Zynq7000: remove csr definition and GP0 connection to the SoC: now handled by zynq700 core CPU
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2024-06-19 07:59:24 +02:00 |
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ebaz4205.py
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…
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efinix_t8f81_dev_kit.py
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targets: Switch to LiteX byte size definitions.
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2024-06-13 10:04:19 +02:00 |
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efinix_titanium_ti60_f225_dev_kit.py
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target/efinix_ti60_f225: Add L2 Cache (16KB for now) to improve perfs/Coremark.
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2024-04-23 11:45:07 +02:00 |
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efinix_trion_t20_bga256_dev_kit.py
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targets: efinix_trion_t20_bga256_dev_kit: add pulse for reset
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2024-06-24 09:14:55 +02:00 |
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efinix_trion_t20_mipi_dev_kit.py
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…
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efinix_trion_t120_bga576_dev_kit.py
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…
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efinix_xyloni_dev_kit.py
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targets: Switch to LiteX byte size definitions.
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2024-06-13 10:04:19 +02:00 |
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ego1.py
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…
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enclustra_mercury_kx2.py
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targets/enclustra: Add Enclustra to identifier.
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2024-07-22 11:38:22 +02:00 |
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enclustra_mercury_xu5.py
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targets/enclustra: Add Enclustra to identifier.
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2024-07-22 11:38:22 +02:00 |
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enclustra_mercury_xu8_pe3.py
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targets: Add initial Enclustra Mercury+ XU8/PE3 target with DRAM and PCIe.
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2024-07-22 11:40:19 +02:00 |
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fairwaves_xtrx.py
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…
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fpc_iii.py
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…
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fpgawars_alhambra2.py
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targets: Switch to LiteX byte size definitions.
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2024-06-13 10:04:19 +02:00 |
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gadgetfactory_papilio_pro.py
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…
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gsd_butterstick.py
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…
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gsd_orangecrab.py
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gsd_orangecrab: Add --without_dfu_rst argument to allow disabling reset to DFU on Button press.
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2024-03-11 17:23:42 +01:00 |
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hackaday_hadbadge.py
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…
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hseda_xc7a35t.py
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Add HSEDA XC7A35T board support
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2024-05-21 21:00:27 +08:00 |
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ice_v_wireless.py
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targets: Switch to LiteX byte size definitions.
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2024-06-13 10:04:19 +02:00 |
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icebreaker.py
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targets: Switch to LiteX byte size definitions.
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2024-06-13 10:04:19 +02:00 |
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icebreaker_bitsy.py
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targets: Switch to LiteX byte size definitions.
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2024-06-13 10:04:19 +02:00 |
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isx_im1283.py
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…
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jungle_electronics_fireant.py
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targets: Switch to LiteX byte size definitions.
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2024-06-13 10:04:19 +02:00 |
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kosagi_fomu.py
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targets: Switch to LiteX byte size definitions.
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2024-06-13 10:04:19 +02:00 |
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kosagi_netv2.py
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…
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krtkl_snickerdoodle.py
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targets: All boards based on Zynq7000: remove csr definition and GP0 connection to the SoC: now handled by zynq700 core CPU
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2024-06-19 07:59:24 +02:00 |
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lambdaconcept_ecpix5.py
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targets/lambdaconcept_ecpix5.py: allows configuring eth_ip/remote_ip/dynamic
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2024-06-14 15:58:25 +02:00 |
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lattice_certuspro_nx_evn.py
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targets/lattice_certuspro_nx_xx,targets/lattice_crosslink_nx_xxx: pass platform to NXOSCA CTOR
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2024-07-22 15:18:27 +02:00 |
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lattice_certuspro_nx_vvml.py
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targets/lattice_certuspro_nx_xx,targets/lattice_crosslink_nx_xxx: pass platform to NXOSCA CTOR
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2024-07-22 15:18:27 +02:00 |
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lattice_crosslink_nx_evn.py
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targets/lattice_certuspro_nx_xx,targets/lattice_crosslink_nx_xxx: pass platform to NXOSCA CTOR
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2024-07-22 15:18:27 +02:00 |
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lattice_crosslink_nx_vip.py
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targets/lattice_certuspro_nx_xx,targets/lattice_crosslink_nx_xxx: pass platform to NXOSCA CTOR
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2024-07-22 15:18:27 +02:00 |
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lattice_ecp5_evn.py
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…
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lattice_ecp5_vip.py
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…
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lattice_ice40up5k_evn.py
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targets: Map SPRAM to SRAM when use as SRAM.
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2024-07-17 11:01:34 +02:00 |
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lattice_versa_ecp5.py
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…
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limesdr_mini_v2.py
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targets/limesdr_mini_v2.py: allows using jtag_uart and added a note to load a demo firmware with litex_term + jtag_uart
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2024-04-11 15:12:17 +02:00 |
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linsn_rv901t.py
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…
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litex_acorn_baseboard.py
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…
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litex_acorn_baseboard_mini.py
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targets/litex_acorn_baseboard_mini: Add detect_ftdi_chip method since newer batch of baseboard is mounted with FTDI ft4232 chips.
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2024-07-19 15:43:25 +02:00 |
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logicbone.py
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…
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machdyne_konfekt.py
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machdyne: switch to LiteXArgumentParser; add mozart ml2+mx1 and vivaldi ml1
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2024-06-22 11:26:43 +02:00 |
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machdyne_kopflos.py
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machdyne: switch to LiteXArgumentParser; add mozart ml2+mx1 and vivaldi ml1
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2024-06-22 11:26:43 +02:00 |
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machdyne_krote.py
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targets: Switch to LiteX byte size definitions.
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2024-06-13 10:04:19 +02:00 |
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machdyne_lakritz.py
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machdyne: switch to LiteXArgumentParser; add mozart ml2+mx1 and vivaldi ml1
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2024-06-22 11:26:43 +02:00 |
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machdyne_minze.py
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machdyne: switch to LiteXArgumentParser; add mozart ml2+mx1 and vivaldi ml1
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2024-06-22 11:26:43 +02:00 |
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machdyne_mozart_ml1.py
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machdyne: switch to LiteXArgumentParser; add mozart ml2+mx1 and vivaldi ml1
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2024-06-22 11:26:43 +02:00 |
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machdyne_mozart_ml2.py
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machdyne: switch to LiteXArgumentParser; add mozart ml2+mx1 and vivaldi ml1
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2024-06-22 11:26:43 +02:00 |
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machdyne_mozart_mx1.py
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machdyne: switch to LiteXArgumentParser; add mozart ml2+mx1 and vivaldi ml1
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2024-06-22 11:26:43 +02:00 |
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machdyne_noir.py
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machdyne: switch to LiteXArgumentParser; add mozart ml2+mx1 and vivaldi ml1
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2024-06-22 11:26:43 +02:00 |
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machdyne_schoko.py
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…
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machdyne_vanille.py
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targets/machdyne_vanille: set uart_name to stub
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2024-06-22 12:13:30 +02:00 |
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machdyne_vivaldi_ml1.py
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machdyne: switch to LiteXArgumentParser; add mozart ml2+mx1 and vivaldi ml1
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2024-06-22 11:26:43 +02:00 |
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micronova_mercury2.py
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targets: Switch to LiteX byte size definitions.
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2024-06-13 10:04:19 +02:00 |
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mist.py
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…
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mnt_rkx7.py
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…
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muselab_icesugar.py
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targets: Map SPRAM to SRAM when use as SRAM.
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2024-07-17 11:01:34 +02:00 |
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muselab_icesugar_pro.py
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…
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myminieye_runber.py
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…
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newae_cw305.py
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…
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numato_aller.py
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…
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numato_mimas_a7.py
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…
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numato_nereid.py
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…
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numato_tagus.py
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…
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ocp_tap_timecard.py
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…
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olimex_gatemate_a1_evb.py
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Olimex GateMate A1 EVB: new Board
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2024-03-02 12:23:27 +01:00 |
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opalkelly_xem8320.py
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…
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pano_logic_g2.py
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…
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qmtech_5cefa2.py
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…
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qmtech_5cefa5.py
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qmtech altera boards: sdram io properties for more speed
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2024-03-30 20:43:41 +07:00 |
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qmtech_10cl006.py
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…
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qmtech_artix7_fbg484.py
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qmtech_artix7_fgg676: fix wrong memory chip type
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2024-03-29 08:41:19 +07:00 |
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qmtech_artix7_fgg676.py
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qmtech_artix7_fgg676: fix wrong memory chip type
|
2024-03-29 08:41:19 +07:00 |
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qmtech_ep4ce15_starter_kit.py
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…
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qmtech_ep4cex5.py
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…
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qmtech_ep4cgx150.py
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qmtech altera boards: sdram io properties for more speed
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2024-03-30 20:43:41 +07:00 |
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qmtech_kintex7_devboard.py
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target/qmtech_kintex7_devboard: +X.
|
2024-02-26 15:41:09 +01:00 |
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qmtech_wukong.py
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qmtech_wukong: Switch to direct instance of LiteEthPHYGMII since hybrid MII/GMII does not seems to work correctly.
|
2024-03-28 16:02:55 +01:00 |
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qmtech_xc7a35t.py
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…
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qmtech_xc7k325t.py
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QMTech XC7K325T: use the buttons on the core board
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2024-02-28 04:40:17 +07:00 |
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quicklogic_quickfeather.py
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targets/quicklogic_quickfeather: updated qlal4s3b_cell_macro Clock and Reset signals (similar fix to #1797)
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2024-05-30 08:37:14 +02:00 |
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qwertyembedded_beaglewire.py
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targets: Switch to LiteX byte size definitions.
|
2024-06-13 10:04:19 +02:00 |
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radiona_ulx3s.py
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…
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radiona_ulx4m_ld_v2.py
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…
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rcs_arctic_tern_bmc_card.py
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…
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redpitaya.py
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targets: All boards based on Zynq7000: remove csr definition and GP0 connection to the SoC: now handled by zynq700 core CPU
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2024-06-19 07:59:24 +02:00 |
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rz_easyfpga.py
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…
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saanlima_pipistrello.py
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…
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scarabhardware_minispartan6.py
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…
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seeedstudio_spartan_edge_accelerator.py
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…
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siglent_sds1104xe.py
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siglent_sdr1104xe: Update IP/MAC addresses.
|
2024-07-02 17:09:23 +02:00 |
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simple.py
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…
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sipeed_tang_mega_138k_pro.py
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Finish tang_mega_138k renaming to tang_mega_138k_pro.
|
2024-03-26 21:58:02 +01:00 |
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sipeed_tang_nano.py
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target/xxx: remove with-uartbone, add_uartbone and deal with case where uartbone is required inconditionnally
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2023-10-23 17:43:13 +02:00 |
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sipeed_tang_nano_4k.py
|
targets: Switch to LiteX byte size definitions.
|
2024-06-13 10:04:19 +02:00 |
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sipeed_tang_nano_9k.py
|
targets: Switch to LiteX byte size definitions.
|
2024-06-13 10:04:19 +02:00 |
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sipeed_tang_nano_20k.py
|
…
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sipeed_tang_primer.py
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…
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sipeed_tang_primer_20k.py
|
…
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sipeed_tang_primer_25k.py
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…
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sitlinv_a_e115fb.py
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…
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sitlinv_stlv7325_v1.py
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…
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sitlinv_stlv7325_v2.py
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…
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sitlinv_xc7k420t.py
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…
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sqrl_acorn.py
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…
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sqrl_fk33.py
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…
|
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sqrl_xcu1525.py
|
…
|
|
|
terasic_de0nano.py
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…
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terasic_de1soc.py
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…
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terasic_de2_115.py
|
terasic_de2_115: Cosmetic cleanup.
|
2023-11-06 19:21:53 +01:00 |
|
terasic_de10lite.py
|
…
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|
|
terasic_de10nano.py
|
…
|
|
|
terasic_deca.py
|
target/xxx: remove with-uartbone, add_uartbone and deal with case where uartbone is required inconditionnally
|
2023-10-23 17:43:13 +02:00 |
|
terasic_sockit.py
|
…
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|
tinyfpga_bx.py
|
targets: Switch to LiteX byte size definitions.
|
2024-06-13 10:04:19 +02:00 |
|
trellisboard.py
|
…
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trenz_c10lprefkit.py
|
…
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|
trenz_cyc1000.py
|
…
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|
trenz_max1000.py
|
…
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trenz_te0725.py
|
…
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|
trenz_tec0117.py
|
targets: Switch to LiteX byte size definitions.
|
2024-06-13 10:04:19 +02:00 |
|
tul_pynq_z2.py
|
…
|
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|
xilinx_ac701.py
|
…
|
|
|
xilinx_alveo_u200.py
|
…
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xilinx_alveo_u250.py
|
…
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xilinx_alveo_u280.py
|
…
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xilinx_kc705.py
|
xilinx_kc705: Minor Cleanup/Update.
|
2024-03-27 08:48:05 +01:00 |
|
xilinx_kcu105.py
|
…
|
|
|
xilinx_kv260.py
|
targets/alinx_axu2cga,xilinx_zcu216,xilinx_kv260: remove csr definition and GP0 connection to the SoC: now handled by znqmp core CPU
|
2024-06-19 07:54:50 +02:00 |
|
xilinx_vc707.py
|
…
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|
xilinx_vcu118.py
|
…
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|
|
xilinx_vcu128.py
|
…
|
|
|
xilinx_zc706.py
|
platforms,targets/xilinx_zc706: added choice between vivado(default) and openFPGALoader, re-enable DDR
|
2024-04-08 20:38:09 +02:00 |
|
xilinx_zcu102.py
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…
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|
xilinx_zcu104.py
|
…
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|
xilinx_zcu106.py
|
…
|
|
|
xilinx_zcu216.py
|
targets/alinx_axu2cga,xilinx_zcu216,xilinx_kv260: remove csr definition and GP0 connection to the SoC: now handled by znqmp core CPU
|
2024-06-19 07:54:50 +02:00 |
|
xilinx_zybo_z7.py
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targets: All boards based on Zynq7000: remove csr definition and GP0 connection to the SoC: now handled by zynq700 core CPU
|
2024-06-19 07:59:24 +02:00 |
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ztex213.py
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…
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