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Florent Kermarrec beccecf59f orangecrab: reduce DDR3 power consumption/heat and get back USB PLL to CRGSDRAM. 
- disable DQ termination.
- disable RTT_NOM.
- drive VCCIO/GND pads.

Reduce current from 0.25A to 0.12A with: ./orangecrab.py --uart-name=usb_acm --sys-clk-freq=48e6.
Still working at 96MHz, 0.17A with: ./orangecrab.py --uart-name=usb_acm --sys-clk-freq=96e6.

See https://github.com/enjoy-digital/litedram/issues/216.
 		2020-08-28 20:01:54 +02:00
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platforms orangecrab: reduce DDR3 power consumption/heat and get back USB PLL to CRGSDRAM. 2020-08-28 20:01:54 +02:00
prog platforms/genesys2: add openocd specific configuration (channel 1 used for JTAG). 2020-06-23 11:55:50 +02:00
targets orangecrab: reduce DDR3 power consumption/heat and get back USB PLL to CRGSDRAM. 2020-08-28 20:01:54 +02:00
tools general: add SPDX License identifier to header and specify files are part of LiteX-Boards. 2020-08-23 15:00:17 +02:00
__init__.py init repo with litex official boards 2019-06-10 17:11:36 +02:00