beccecf59f
orangecrab: reduce DDR3 power consumption/heat and get back USB PLL to CRGSDRAM.
...
- disable DQ termination.
- disable RTT_NOM.
- drive VCCIO/GND pads.
Reduce current from 0.25A to 0.12A with: ./orangecrab.py --uart-name=usb_acm --sys-clk-freq=48e6.
Still working at 96MHz, 0.17A with: ./orangecrab.py --uart-name=usb_acm --sys-clk-freq=96e6.
See https://github.com/enjoy-digital/litedram/issues/216 .
2020-08-28 20:01:54 +02:00
63b65e278c
crosslink_nx_evn: update copyrights.
2020-08-24 22:33:58 +02:00
153326fa26
targets/icebreaker: update flash.
2020-08-24 17:19:15 +02:00
795e34aafd
add initial Crosslink-NX support.
2020-08-24 16:47:38 +02:00
84c19a6cdf
targets/de0nano: set sys2x_ps phase to 180° for sdram_rate=1:2.
2020-08-24 09:28:51 +02:00
70594a5305
ulx3s: simplify sdram constraints and increase phase to 180 for sdram_rate=1:2.
2020-08-24 09:05:58 +02:00
1781be166a
general: add SPDX License identifier to header and specify files are part of LiteX-Boards.
2020-08-23 15:00:17 +02:00
83d8b8d1b4
platforms/acorn_cle_215: integrated sdcard ios as extension.
2020-08-22 22:11:51 +02:00
f328909578
Moved platform call inside of BaseSoC init for compatibility with linux-on-litex-vexriscv support. Added optional spi-sdcard support over P2 header.
2020-08-09 16:27:41 -04:00
45bb329b56
targets/colorlight_5a_75x: enable HalfRate SDRAM PHY.
2020-08-07 19:26:12 +02:00
b6a1ad5a9c
targets/orangecrab: add simple CRG when built without DDR3.
2020-08-07 18:10:03 +02:00
869ceadacb
targets: use platform.request_all on LedChaser.
2020-08-06 20:04:03 +02:00
d2cd6d4c0e
arty: Change USB-uart and I2S Pmod configuration
...
This makes it compatible with the Arty A7 expansion board by Antmicro
(https://github.com/antmicro/arty-expansion-board ).
2020-08-05 11:54:25 +02:00
ee28d7b5ec
targets/ulx3s/add_oled: simplify.
2020-08-04 12:31:15 +02:00
eba70377b7
add optional OLED peripheral to ULX3S target
2020-08-04 11:07:30 +02:00
929e55d7e6
platforms/trellisboard: add SDCard PMOD pins.
2020-07-29 09:07:55 +02:00
5fd3e8dbcd
ecpix5: add SDCard.
...
Validated with Linux-on-LiteX-VexRiscv.
2020-07-28 17:45:49 +02:00
94ccf1dd3e
targets/trellisboard: simplify clocking when no DDR3, remove firmware_ram (was here for debug).
2020-07-27 16:31:46 +02:00
eb8a484032
targets/de10nano: fix typo.
2020-07-26 12:01:11 +02:00
2cef54a909
targets/colorlight_5a_75x: avoid sys_clk_freq of 125MHz with etherbone (no longer required).
...
This allows creating SoCs with CPU, SDRAM and Etherbone enabled all together.
2020-07-26 11:58:42 +02:00
760b8ff93a
arty: improve xy_pmod_io genericity (allow selecting the PMOD) and enable SDCard.
2020-07-24 16:29:35 +02:00
04fc98f834
de0nano/ulx3s: add sdram HalfRate support (untested).
2020-07-24 16:12:46 +02:00
d0ca1befa6
targets/de10nano/minispartan6: simplify HalfRate support, rename argument to sdram_rate.
2020-07-24 16:11:57 +02:00
9730c6f722
platforms/de10nano: use additional sdram constraints required for HalfRate.
2020-07-24 12:27:36 +02:00
7399d13cef
paltforms/de10nano/sdram: enable fast input/output on dq.
2020-07-24 11:27:25 +02:00
b4b1ab8621
paltforms/de10nano: simplify IO constraints (for consistency with others platforms).
2020-07-24 09:03:35 +02:00
89c5bf43cf
Merge pull request #92 from rob-ng15/master
...
Enable use of HalfRateGENSDRPHY on de10nano
2020-07-24 08:49:09 +02:00
1e1589a514
zybo_z7: demonstrate use of PS7 (with --cpu-type=zynq7000).
...
This uses a pre-generated .xci hosted on github, still need to figure out where the best location for it.
2020-07-23 17:45:21 +02:00
7cda143250
Allow use of HalfRateGENSDRPHY
2020-07-23 14:41:35 +01:00
cf9839307f
Add Misc
...
Add Misc("") arguments to various inputs/outputs for stability. Allows de10nano to use HalfRateGENSDRPHY for sdram
2020-07-23 14:40:04 +01:00
8a3b453e2f
add Zybo Z7 minimal platform/targets: no PS7 support and USB-UART PMOD on JB.
2020-07-23 15:26:22 +02:00
e723bef49a
platforms/arty: add usb_uart_pmod_io (USB-UART PMOD on JA) to ease debug with a second UART (for UARTbone/LiteScope).
...
Also use pmod connector names in i2s_pmod and sdcard_pmod.
2020-07-22 14:41:09 +02:00
19d0b95867
platforms/targets: keep in sync with litex.
2020-07-22 08:53:49 +02:00
0ee4b215b9
trellisboard/ulx3s: fix sdcard slewrate.
2020-07-21 15:23:08 +02:00
7efa1c37a1
platforms/arty: add missing pullups on sdcard.
2020-07-21 15:22:39 +02:00
2ce24df76d
platforms/genesys2: add internal_vref to 0.750v on bank 34 (DDR3).
2020-07-18 22:18:41 +02:00
135c387155
platforms/ulx3s: add assertion for supported devices.
2020-07-17 12:04:06 +02:00
851378f0a9
platforms/trellisboard: move ddram_vtt_en.
2020-07-17 12:03:37 +02:00
165f9eacde
Merge pull request #91 from antmicro/jboc/gensdrphy
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targets/minispartan6: add support for HalfRateGENSDRPHY
2020-07-15 08:22:57 +02:00
02f53e6326
targets/minispartan6: add support for HalfRateGENSDRPHY
2020-07-14 11:01:09 +02:00
44ad902aad
platforms/kc705.py: LPC DP0_M2C/C2M diff pair
2020-07-13 10:26:17 -07:00
a461f5ac59
orangecrab: add usb, rst_n signals for r0.1
...
- fix standard io extensions
- Use newly assigned code for orangecrab 1209:5af0
2020-07-09 19:56:32 +09:30
f3d02d8fca
Merge pull request #87 from antmicro/arty_i2s
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arty: Add configuration of I2S pins
2020-07-07 17:22:10 +02:00
df54b93db3
arty: Add configuration of I2S pins
2020-07-07 15:25:10 +02:00
d9595a317e
targets/orangecrab: use user_btn as rst_n.
2020-07-06 17:49:05 +02:00
40fbbbbebc
platforms/orangecrab: add sdcard pins on r0_2.
2020-07-06 17:48:48 +02:00
7b1bf9d74a
targets: remove sdcard specific clock domain (now generated by the PHY).
2020-07-03 20:09:30 +02:00
31e6997e70
sdcard: rename cd_sdcard to cd_sd to avoid unnecessary clock domain.
2020-07-01 12:58:48 +02:00
fe3ea805bc
targets/pcie: make pcie optional (--with-pcie) and avoid forcing uart to crossover.
2020-06-30 18:44:00 +02:00
7a48a61605
targets: add indentifier on all targets.
2020-06-30 18:11:04 +02:00
Florent Kermarrec
Piense
connorwk
Pawel Sagan
Pepijn de Vos
rob-ng15
Jędrzej Boczar
Vamsi K Vytla
Greg Davill