aaf8d54c6a
At the start output of the pll is not stabilized, which caused malfunctions when used for sys clock domain. Use AsyncResetSynchronizer to start clock domains on pll locked signal. |
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.. | ||
__init__.py | ||
ac701.py | ||
de1soc.py | ||
de2_115.py | ||
de10lite.py | ||
ecp5_evn.py | ||
pipistrello.py |