2015-01-28 18:25:55 -05:00
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from liteeth.common import *
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2015-02-10 09:11:06 -05:00
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from liteeth.core.udp.common import *
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2015-01-28 18:25:55 -05:00
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2015-02-04 14:50:49 -05:00
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class LiteEthUDPTX(Module):
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def __init__(self, ip_address):
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2015-02-09 03:26:56 -05:00
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self.sink = sink = Sink(eth_udp_user_description(8))
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self.source = source = Source(eth_ipv4_user_description(8))
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2015-02-04 14:50:49 -05:00
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###
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2015-02-09 03:26:56 -05:00
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self.submodules.packetizer = packetizer = LiteEthUDPPacketizer()
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2015-02-04 14:50:49 -05:00
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self.comb += [
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2015-02-09 03:26:56 -05:00
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packetizer.sink.stb.eq(sink.stb),
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packetizer.sink.sop.eq(sink.sop),
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packetizer.sink.eop.eq(sink.eop),
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sink.ack.eq(packetizer.sink.ack),
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packetizer.sink.src_port.eq(sink.src_port),
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packetizer.sink.dst_port.eq(sink.dst_port),
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packetizer.sink.length.eq(sink.length + udp_header_len),
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packetizer.sink.checksum.eq(0), # Disabled (MAC CRC is enough)
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packetizer.sink.data.eq(sink.data)
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2015-02-04 14:50:49 -05:00
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]
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2015-02-05 05:58:40 -05:00
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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2015-02-04 14:50:49 -05:00
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fsm.act("IDLE",
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2015-02-09 03:26:56 -05:00
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packetizer.source.ack.eq(1),
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If(packetizer.source.stb & packetizer.source.sop,
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packetizer.source.ack.eq(0),
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2015-02-04 14:50:49 -05:00
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NextState("SEND")
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)
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)
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fsm.act("SEND",
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2015-02-09 03:26:56 -05:00
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Record.connect(packetizer.source, source),
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source.length.eq(packetizer.sink.length),
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source.protocol.eq(udp_protocol),
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source.ip_address.eq(sink.ip_address),
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If(source.stb & source.eop & source.ack,
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2015-02-04 14:50:49 -05:00
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NextState("IDLE")
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)
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)
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class LiteEthUDPRX(Module):
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def __init__(self, ip_address):
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2015-02-09 03:26:56 -05:00
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self.sink = sink = Sink(eth_ipv4_user_description(8))
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2015-02-04 14:50:49 -05:00
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self.source = source = Source(eth_udp_user_description(8))
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###
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2015-02-09 03:26:56 -05:00
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self.submodules.depacketizer = depacketizer = LiteEthUDPDepacketizer()
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self.comb += Record.connect(sink, depacketizer.sink)
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2015-02-04 14:50:49 -05:00
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2015-02-05 05:58:40 -05:00
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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2015-02-04 14:50:49 -05:00
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fsm.act("IDLE",
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2015-02-09 03:26:56 -05:00
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depacketizer.source.ack.eq(1),
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If(depacketizer.source.stb & depacketizer.source.sop,
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depacketizer.source.ack.eq(0),
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2015-02-04 14:50:49 -05:00
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NextState("CHECK")
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)
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)
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valid = Signal()
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2015-02-09 08:49:59 -05:00
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self.sync += valid.eq(
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2015-02-09 03:26:56 -05:00
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depacketizer.source.stb &
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(sink.protocol == udp_protocol)
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2015-02-04 14:50:49 -05:00
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)
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fsm.act("CHECK",
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If(valid,
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NextState("PRESENT")
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).Else(
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NextState("DROP")
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)
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2015-02-05 18:29:30 -05:00
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)
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self.comb += [
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2015-02-09 03:26:56 -05:00
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source.sop.eq(depacketizer.source.sop),
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source.eop.eq(depacketizer.source.eop),
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source.src_port.eq(depacketizer.source.src_port),
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source.dst_port.eq(depacketizer.source.dst_port),
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source.ip_address.eq(sink.ip_address),
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source.length.eq(depacketizer.source.length - udp_header_len),
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source.data.eq(depacketizer.source.data),
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source.error.eq(depacketizer.source.error)
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2015-02-05 18:29:30 -05:00
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]
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fsm.act("PRESENT",
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source.stb.eq(depacketizer.source.stb),
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depacketizer.source.ack.eq(source.ack),
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2015-02-04 14:50:49 -05:00
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If(source.stb & source.eop & source.ack,
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NextState("IDLE")
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)
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)
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fsm.act("DROP",
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2015-02-09 03:26:56 -05:00
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depacketizer.source.ack.eq(1),
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If(depacketizer.source.stb & depacketizer.source.eop & depacketizer.source.ack,
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2015-02-04 14:50:49 -05:00
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NextState("IDLE")
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)
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)
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class LiteEthUDP(Module):
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2015-02-09 05:19:26 -05:00
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def __init__(self, ip, ip_address):
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2015-02-09 03:26:56 -05:00
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self.submodules.tx = tx = LiteEthUDPTX(ip_address)
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self.submodules.rx = rx = LiteEthUDPRX(ip_address)
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2015-02-05 18:54:05 -05:00
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ip_port = ip.crossbar.get_port(udp_protocol)
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2015-02-04 15:15:01 -05:00
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self.comb += [
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2015-02-09 03:26:56 -05:00
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Record.connect(tx.source, ip_port.sink),
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Record.connect(ip_port.source, rx.sink)
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2015-02-04 15:15:01 -05:00
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]
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2015-02-09 05:19:26 -05:00
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self.submodules.crossbar = crossbar = LiteEthUDPCrossbar()
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self.comb += [
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Record.connect(crossbar.master.source, tx.sink),
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Record.connect(rx.source, crossbar.master.sink)
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]
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