litex/litex/build/altera/quartus.py

# This file is Copyright (c) 2014-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# This file is Copyright (c) 2019 msloniewski <marcin.sloniewski@gmail.com>
# This file is Copyright (c) 2019 vytautasb <v.buitvydas@limemicro.com>
# License: BSD

import os
import subprocess
import sys
import math

from migen.fhdl.structure import _Fragment

from litex.build.generic_platform import Pins, IOStandard, Misc
from litex.build import tools


def _format_constraint(c, signame, fmt_r):
    if isinstance(c, Pins):
        return "set_location_assignment -comment \"{name}\" " \
            "-to {signame} Pin_{pin}".format(
                signame=signame,
                name=fmt_r,
                pin=c.identifiers[0])
    elif isinstance(c, IOStandard):
        return "set_instance_assignment -name io_standard " \
            "-comment \"{name}\" \"{std}\" -to {signame}".format(
                signame=signame,
                name=fmt_r,
                std=c.name)
    elif isinstance(c, Misc):
        if not isinstance(c.misc, str) and len(c.misc) == 2:
            return "set_instance_assignment -comment \"{name}\" " \
                "-name {misc[0]} \"{misc[1]}\" -to {signame}".format(
                    signame=signame,
                    name=fmt_r,
                    misc=c.misc)
        else:
            return "set_instance_assignment -comment \"{name}\" " \
                "-name {misc} " \
                "-to {signame}".format(
                    signame=signame,
                    name=fmt_r,
                    misc=c.misc)


def _format_qsf(signame, pin, others, resname):
    fmt_r = "{}:{}".format(*resname[:2])
    if resname[2] is not None:
        fmt_r += "." + resname[2]

    fmt_c = [_format_constraint(c, signame, fmt_r) for c in
             ([Pins(pin)] + others)]

    return '\n'.join(fmt_c)


def _build_qsf(named_sc, named_pc, build_name):
    lines = []
    for sig, pins, others, resname in named_sc:
        if len(pins) > 1:
            for i, p in enumerate(pins):
                lines.append(
                    _format_qsf("{}[{}]".format(sig, i), p, others, resname))
        else:
            lines.append(_format_qsf(sig, pins[0], others, resname))

    if named_pc:
        lines.append("")
        lines.append("\n\n".join(named_pc))

    # Set top level name to "build_name" in .qsf file instead always use "top" name
    lines.append("set_global_assignment -name top_level_entity " + build_name)
    return "\n".join(lines)


def _build_sdc(clocks, false_paths, vns, build_name):
    lines = []
    for clk, period in sorted(clocks.items(), key=lambda x: x[0].duid):
        lines.append(
            "create_clock -name {clk} -period ".format(clk=vns.get_name(clk)) + str(period) +
            " [get_ports {{{clk}}}]".format(clk=vns.get_name(clk)))
    for from_, to in sorted(false_paths,
                            key=lambda x: (x[0].duid, x[1].duid)):
        lines.append(
            "set_false_path "
            "-from [get_clocks {{{from_}}}] "
            "-to [get_clocks {{{to}}}]".format(
            from_=vns.get_name(from_), to=vns.get_name(to)))
    tools.write_to_file("{}.sdc".format(build_name), "\n".join(lines))


def _build_files(device, ips, sources, vincpaths, named_sc, named_pc, build_name):
    lines = []
    for filename in ips:
           lines.append("set_global_assignment -name QSYS_FILE {path} ".format(
                path=filename.replace("\\", "/")))
    for filename, language, library in sources:
        # Enforce use of SystemVerilog since Quartus does not support global parameters in Verilog
        if language == "verilog":
            language = "systemverilog"
        lines.append(
            "set_global_assignment -name {lang}_FILE {path} "
            "-library {lib}".format(
                lang=language.upper(),
                path=filename.replace("\\", "/"),
                lib=library))
    lines.append("set_global_assignment -name SDC_FILE {}.sdc".format(build_name))

    for path in vincpaths:
        lines.append("set_global_assignment -name SEARCH_PATH {}".format(
            path.replace("\\", "/")))

    lines.append(_build_qsf(named_sc, named_pc, build_name))
    lines.append("set_global_assignment -name DEVICE {}".format(device))
    tools.write_to_file("{}.qsf".format(build_name), "\n".join(lines))


def _run_quartus(build_name, quartus_path, create_rbf):
    if sys.platform == "win32" or sys.platform == "cygwin":
        build_script_contents = "REM Autogenerated by LiteX / git: " + tools.get_litex_git_revision() + "\n"
        build_script_file = "build_" + build_name + ".bat"
        command = build_script_file
    else:
        build_script_contents = "# Autogenerated by LiteX / git: " + tools.get_litex_git_revision() + "\nset -e\n"
        build_script_file = "build_" + build_name + ".sh"
        command = ["bash", build_script_file]
    build_script_contents += """

set -e

quartus_map --read_settings_files=on --write_settings_files=off {build_name} -c {build_name}
quartus_fit --read_settings_files=off --write_settings_files=off {build_name} -c {build_name}
quartus_asm --read_settings_files=off --write_settings_files=off {build_name} -c {build_name}
quartus_sta {build_name} -c {build_name}"""
    if create_rbf:
        build_script_contents +="""
if [ -f "{build_name}.sof" ]
then
    quartus_cpf -c {build_name}.sof {build_name}.rbf
fi

"""
    build_script_contents = build_script_contents.format(build_name=build_name)  # noqa
    tools.write_to_file(build_script_file,
                        build_script_contents,
                        force_unix=True)

    if subprocess.call(command):
        raise OSError("Subprocess failed")


class AlteraQuartusToolchain:
    def __init__(self):
        self.clocks = dict()
        self.false_paths = set()

    def build(self, platform, fragment, build_dir="build", build_name="top",
              toolchain_path=None, run=True, **kwargs):
        if toolchain_path is None:
            toolchain_path="/opt/Altera"
        cwd = os.getcwd()
        os.makedirs(build_dir, exist_ok=True)
        os.chdir(build_dir)

        if not isinstance(fragment, _Fragment):
            fragment = fragment.get_fragment()
        platform.finalize(fragment)

        v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
        named_sc, named_pc = platform.resolve_signals(v_output.ns)
        v_file = build_name + ".v"
        v_output.write(v_file)
        platform.add_source(v_file)
        _build_files(platform.device,
                     platform.ips,
                     platform.sources,
                     platform.verilog_include_paths,
                     named_sc,
                     named_pc,
                     build_name)

        _build_sdc(self.clocks, self.false_paths, v_output.ns, build_name)
        if run:
            _run_quartus(build_name, toolchain_path, platform.create_rbf)

        os.chdir(cwd)

        return v_output.ns

    def add_period_constraint(self, platform, clk, period):
        if clk in self.clocks:
            raise ValueError("A period constraint already exists")
        period = math.floor(period*1e3)/1e3 # round to lowest picosecond
        self.clocks[clk] = period

    def add_false_path_constraint(self, platform, from_, to):
        if (to, from_) not in self.false_paths:
            self.false_paths.add((from_, to))