Florent Kermarrec
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6e6fe83af3
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build/altera/quartus: add add_ip method to use Quartus QSYS files
platform.add_ip("my_ip.qsys")
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2019-08-15 13:45:29 +02:00 |
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Florent Kermarrec
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a496760cb6
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build/altera/quartus: use .bat on win32/cygwin
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2019-08-02 10:27:38 +02:00 |
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Florent Kermarrec
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daa4307d9e
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add CONTRIBUTORS file and add copyright header to all files
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2019-06-23 23:23:56 +02:00 |
msloniewski
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a826aacac0
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build/altera: Add possibility to turn off generation of .rbf file
For some FPGAs (e.g. MAX10) .rbf file cannot be generated.
Add possibility to turn off that feature for those chips.
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2019-06-05 18:57:59 +02:00 |
|
Florent Kermarrec
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475deb51ac
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build: add migen and litex git revision to generated file
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2019-04-23 17:40:24 +02:00 |
|
Florent Kermarrec
|
425741226c
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build: add sha-1/date to generated verilog, change git_version to git_revision
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2019-04-23 12:59:25 +02:00 |
|
Florent Kermarrec
|
eff141da2d
|
build: add git version (sha-1) used to create the scripts
|
2019-04-23 06:03:12 +02:00 |
|
Florent Kermarrec
|
cc141a64b9
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build: scripts are generated by LiteX
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2019-04-23 05:38:33 +02:00 |
|
Florent Kermarrec
|
017147c623
|
build/altera: switch to sdc constraints, add add_false_path_constraints method
|
2019-04-16 16:57:23 +02:00 |
vytautasb
|
04939990ac
|
litex/build/altera/quartus: changes to make top level assigment in .qsf file with build name
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2019-04-08 14:07:10 +03:00 |
|
Florent Kermarrec
|
a7f17f9915
|
build: use default toolchain_path on all backend when passed value is None
|
2018-11-12 11:48:30 +01:00 |
|
Florent Kermarrec
|
665fff8390
|
build: merge more migen changes
|
2018-11-12 11:26:35 +01:00 |
|
Florent Kermarrec
|
cb86728ad1
|
build/lattice: import changes from migen
|
2018-11-12 10:46:49 +01:00 |
|
Florent Kermarrec
|
8a311bf4a6
|
build/generic_platform: use list for sources instead of set
Ideally, we want to use an ordered set (to be able to keep compilation order), to avoid using an external package, we use a list.
|
2018-07-20 10:01:33 +02:00 |
|
Florent Kermarrec
|
1925ba176f
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replace litex.gen imports with migen imports
|
2018-02-23 13:38:19 +01:00 |
|
Florent Kermarrec
|
ff31959aea
|
merge most of misoc 54e1ef82 and migen e93d0601 changes
|
2017-01-13 03:55:00 +01:00 |
|
Florent Kermarrec
|
e8262ed447
|
build: pass build_name to get_verilog (same name for top module and top level file)
|
2015-12-02 14:18:09 +01:00 |
|
Florent Kermarrec
|
53c86e34f4
|
build: ensure we return to working directory after building
|
2015-11-30 13:33:39 +01:00 |
|
Florent Kermarrec
|
fc3ffe87ac
|
for now use our fork of migen (to be able to simulate our designs)
|
2015-11-13 18:31:46 +01:00 |
|
Florent Kermarrec
|
619cd8e695
|
avoid forking migen, we will add custom modules in litex/gen but will use upstream migen for common modules
|
2015-11-11 12:10:55 +01:00 |
|
Florent Kermarrec
|
6a0f85dc42
|
litex: reorganize things, first work working version
|
2015-11-07 17:48:55 +01:00 |