98 lines
4.4 KiB
Python
98 lines
4.4 KiB
Python
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from misoclib.mem.litesata.common import *
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from migen.genlib.cdc import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.bank.description import *
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from misoclib.soc import SoC
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from misoclib.tools.litescope.common import *
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from misoclib.tools.litescope.frontend.la import LiteScopeLA
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from misoclib.tools.litescope.core.port import LiteScopeTerm
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from misoclib.com.uart.bridge import UARTWishboneBridge
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from misoclib.mem.litesata.common import *
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from misoclib.mem.litesata.phy import LiteSATAPHY
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from misoclib.mem.litesata.core import LiteSATACore
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from misoclib.mem.litesata.frontend.crossbar import LiteSATACrossbar
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from misoclib.mem.litesata.frontend.mirroring import LiteSATAMirroring
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from misoclib.mem.litesata.frontend.bist import LiteSATABIST
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from misoclib.mem.litesata.example_designs.targets.bist import CRG, StatusLeds
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class MirroringSoC(SoC, AutoCSR):
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default_platform = "kc705"
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csr_map = {
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"sata_bist0": 16,
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"sata_bist1": 17,
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"sata_bist2": 18,
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"sata_bist3": 19,
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}
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csr_map.update(SoC.csr_map)
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def __init__(self, platform):
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clk_freq = 166*1000000
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SoC.__init__(self, platform, clk_freq,
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cpu_type="none",
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with_csr=True, csr_data_width=32,
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with_uart=False,
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with_identifier=True,
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with_timer=False
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)
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self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
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self.add_wb_master(self.cpu_or_bridge.wishbone)
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self.submodules.crg = CRG(platform)
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# SATA PHYs
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sata_phy0 = LiteSATAPHY(platform.device, platform.request("sata_clocks"), platform.request("sata", 0), "sata_gen2", clk_freq)
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sata_phy1 = LiteSATAPHY(platform.device, sata_phy0.crg.refclk, platform.request("sata", 1), "sata_gen2", clk_freq)
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sata_phy2 = LiteSATAPHY(platform.device, sata_phy0.crg.refclk, platform.request("sata", 2), "sata_gen2", clk_freq)
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sata_phy3 = LiteSATAPHY(platform.device, sata_phy0.crg.refclk, platform.request("sata", 3), "sata_gen2", clk_freq)
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sata_phys = [sata_phy0, sata_phy1, sata_phy2, sata_phy3]
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for i, sata_phy in enumerate(sata_phys):
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sata_phy = RenameClockDomains(sata_phy, {"sata_rx": "sata_rx{}".format(str(i)),
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"sata_tx": "sata_tx{}".format(str(i))})
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setattr(self.submodules, "sata_phy{}".format(str(i)), sata_phy)
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# SATA Cores
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self.submodules.sata_core0 = LiteSATACore(self.sata_phy0)
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self.submodules.sata_core1 = LiteSATACore(self.sata_phy1)
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self.submodules.sata_core2 = LiteSATACore(self.sata_phy2)
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self.submodules.sata_core3 = LiteSATACore(self.sata_phy3)
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sata_cores = [self.sata_core0, self.sata_core1, self.sata_core2, self.sata_core3]
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# SATA Frontend
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self.submodules.sata_mirroring = LiteSATAMirroring(sata_cores)
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self.submodules.sata_crossbar0 = LiteSATACrossbar(self.sata_mirroring.ports[0])
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self.submodules.sata_crossbar1 = LiteSATACrossbar(self.sata_mirroring.ports[1])
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self.submodules.sata_crossbar2 = LiteSATACrossbar(self.sata_mirroring.ports[2])
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self.submodules.sata_crossbar3 = LiteSATACrossbar(self.sata_mirroring.ports[3])
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# SATA Application
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self.submodules.sata_bist0 = LiteSATABIST(self.sata_crossbar0, with_csr=True)
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self.submodules.sata_bist1 = LiteSATABIST(self.sata_crossbar1, with_csr=True)
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self.submodules.sata_bist2 = LiteSATABIST(self.sata_crossbar2, with_csr=True)
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self.submodules.sata_bist3 = LiteSATABIST(self.sata_crossbar3, with_csr=True)
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# Status Leds
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self.submodules.status_leds = StatusLeds(platform, sata_phys)
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platform.add_platform_command("""
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create_clock -name sys_clk -period 6 [get_nets sys_clk]
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""")
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for i in range(len(sata_phys)):
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platform.add_platform_command("""
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create_clock -name {sata_rx_clk} -period 6.66 [get_nets {sata_rx_clk}]
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create_clock -name {sata_tx_clk} -period 6.66 [get_nets {sata_tx_clk}]
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set_false_path -from [get_clocks sys_clk] -to [get_clocks {sata_rx_clk}]
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set_false_path -from [get_clocks sys_clk] -to [get_clocks {sata_tx_clk}]
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set_false_path -from [get_clocks {sata_rx_clk}] -to [get_clocks sys_clk]
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set_false_path -from [get_clocks {sata_tx_clk}] -to [get_clocks sys_clk]
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""".format(sata_rx_clk="sata_rx{}_clk".format(str(i)),
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sata_tx_clk="sata_tx{}_clk".format(str(i))))
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default_subtarget = MirroringSoC
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