2015-09-22 12:36:47 -04:00
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from migen import *
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2012-06-17 11:22:02 -04:00
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from migen.flow.network import *
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2013-11-20 18:33:22 -05:00
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from migen.flow import plumbing
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2014-08-03 00:30:15 -04:00
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from migen.bank.description import AutoCSR
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2015-03-02 02:24:51 -05:00
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from migen.actorlib import structuring, misc
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2012-06-17 11:22:02 -04:00
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2015-09-22 12:35:02 -04:00
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from misoc.mem.sdram.frontend import dma_lasmi
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2015-09-23 12:18:27 -04:00
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from misoc.framebuffer.format import bpp, pixel_layout, FrameInitiator, VTG
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from misoc.framebuffer.phy import Driver
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2012-07-03 13:04:44 -04:00
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2015-04-13 10:47:22 -04:00
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2013-09-17 12:15:22 -04:00
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class Framebuffer(Module, AutoCSR):
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2015-04-13 10:19:55 -04:00
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def __init__(self, pads_vga, pads_dvi, lasmim):
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pack_factor = lasmim.dw//bpp
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2014-10-17 05:14:35 -04:00
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2015-04-13 10:19:55 -04:00
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g = DataFlowGraph()
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2013-11-20 18:33:22 -05:00
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2015-04-13 10:19:55 -04:00
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self.fi = FrameInitiator(lasmim.aw, pack_factor)
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2013-11-20 18:33:22 -05:00
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2015-04-13 10:19:55 -04:00
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intseq = misc.IntSequence(lasmim.aw, lasmim.aw)
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dma_out = AbstractActor(plumbing.Buffer)
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g.add_connection(self.fi, intseq, source_subr=self.fi.dma_subr())
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g.add_pipeline(intseq, AbstractActor(plumbing.Buffer), dma_lasmi.Reader(lasmim), dma_out)
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2013-09-17 12:15:22 -04:00
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2015-04-13 10:19:55 -04:00
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cast = structuring.Cast(lasmim.dw, pixel_layout(pack_factor), reverse_to=True)
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vtg = VTG(pack_factor)
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self.driver = Driver(pack_factor, pads_vga, pads_dvi)
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2014-10-17 05:14:35 -04:00
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2015-04-13 10:19:55 -04:00
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g.add_connection(self.fi, vtg, source_subr=self.fi.timing_subr, sink_ep="timing")
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g.add_connection(dma_out, cast)
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g.add_connection(cast, vtg, sink_ep="pixels")
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g.add_connection(vtg, self.driver)
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self.submodules += CompositeActor(g)
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