litex/migen/bank/csrgen.py

80 lines
2.5 KiB
Python
Raw Normal View History

2011-12-16 15:30:14 -05:00
from migen.fhdl.structure import *
2011-12-16 10:02:55 -05:00
from migen.bus.csr import *
from migen.bank.description import *
2011-12-05 11:43:56 -05:00
class Bank:
def __init__(self, description, address=0):
self.description = description
self.address = address
2012-02-15 10:42:17 -05:00
self.interface = Interface()
2011-12-05 11:43:56 -05:00
2011-12-16 10:02:55 -05:00
def get_fragment(self):
2011-12-05 11:43:56 -05:00
comb = []
sync = []
2011-12-18 15:47:48 -05:00
sel = Signal()
2012-02-15 10:42:17 -05:00
comb.append(sel.eq(self.interface.adr[9:] == Constant(self.address, BV(5))))
2011-12-05 11:43:56 -05:00
desc_exp = expand_description(self.description, 8)
nbits = bits_for(len(desc_exp)-1)
2011-12-05 11:43:56 -05:00
# Bus writes
bwcases = []
for i, reg in enumerate(desc_exp):
2012-02-06 07:55:50 -05:00
if isinstance(reg, RegisterRaw):
2012-02-15 10:42:17 -05:00
comb.append(reg.r.eq(self.interface.dat_w[:reg.size]))
2012-02-06 07:55:50 -05:00
comb.append(reg.re.eq(sel & \
2012-02-15 10:42:17 -05:00
self.interface.we & \
(self.interface.adr[:nbits] == Constant(i, BV(nbits)))))
2012-02-06 07:55:50 -05:00
elif isinstance(reg, RegisterFields):
2011-12-17 18:28:04 -05:00
bwra = [Constant(i, BV(nbits))]
offset = 0
for field in reg.fields:
2011-12-17 18:28:04 -05:00
if field.access_bus == WRITE_ONLY or field.access_bus == READ_WRITE:
2012-02-15 10:42:17 -05:00
bwra.append(field.storage.eq(self.interface.dat_w[offset:offset+field.size]))
offset += field.size
2011-12-17 18:28:04 -05:00
if len(bwra) > 1:
bwcases.append(bwra)
else:
2012-02-06 07:55:50 -05:00
raise TypeError
2011-12-05 11:43:56 -05:00
if bwcases:
2012-02-15 10:42:17 -05:00
sync.append(If(sel & self.interface.we, Case(self.interface.adr[:nbits], *bwcases)))
2011-12-05 11:43:56 -05:00
# Bus reads
brcases = []
for i, reg in enumerate(desc_exp):
2012-02-06 07:55:50 -05:00
if isinstance(reg, RegisterRaw):
2012-02-15 10:42:17 -05:00
brcases.append([Constant(i, BV(nbits)), self.interface.dat_r.eq(reg.w)])
2012-02-06 07:55:50 -05:00
elif isinstance(reg, RegisterFields):
2011-12-17 18:28:04 -05:00
brs = []
reg_readable = False
for field in reg.fields:
2011-12-17 18:28:04 -05:00
if field.access_bus == READ_ONLY or field.access_bus == READ_WRITE:
brs.append(field.storage)
reg_readable = True
else:
brs.append(Constant(0, BV(field.size)))
if reg_readable:
if len(brs) > 1:
2012-02-15 10:42:17 -05:00
brcases.append([Constant(i, BV(nbits)), self.interface.dat_r.eq(Cat(*brs))])
2011-12-17 18:28:04 -05:00
else:
2012-02-15 10:42:17 -05:00
brcases.append([Constant(i, BV(nbits)), self.interface.dat_r.eq(brs[0])])
2011-12-17 18:28:04 -05:00
else:
2012-02-06 07:55:50 -05:00
raise TypeError
2011-12-05 11:43:56 -05:00
if brcases:
2012-02-15 10:42:17 -05:00
sync.append(self.interface.dat_r.eq(Constant(0, BV(8))))
sync.append(If(sel, Case(self.interface.adr[:nbits], *brcases)))
2011-12-05 11:43:56 -05:00
else:
2012-02-15 10:42:17 -05:00
comb.append(self.interface.dat_r.eq(Constant(0, BV(8))))
2011-12-05 11:43:56 -05:00
# Device access
for reg in self.description:
2012-02-06 07:55:50 -05:00
if isinstance(reg, RegisterFields):
2011-12-17 18:28:04 -05:00
for field in reg.fields:
if field.access_dev == READ_ONLY or field.access_dev == READ_WRITE:
2012-02-06 07:55:50 -05:00
comb.append(field.r.eq(field.storage))
2011-12-17 18:28:04 -05:00
if field.access_dev == WRITE_ONLY or field.access_dev == READ_WRITE:
2012-02-06 07:55:50 -05:00
sync.append(If(field.we, field.storage.eq(field.w)))
2011-12-05 11:43:56 -05:00
2011-12-16 15:30:14 -05:00
return Fragment(comb, sync)