2012-01-06 18:33:28 -05:00
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import networkx as nx
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2011-12-22 18:36:07 -05:00
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from migen.fhdl import verilog
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from migen.flow.ala import *
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2012-01-06 18:33:28 -05:00
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from migen.flow.network import *
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2012-01-08 07:56:11 -05:00
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from migen.flow.composer import *
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2012-01-06 11:24:05 -05:00
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2012-01-06 18:33:28 -05:00
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g = nx.MultiDiGraph()
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2012-01-08 07:56:11 -05:00
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a1 = make_composable(g, Add(BV(16)))
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a2 = make_composable(g, Add(BV(16)))
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a3 = make_composable(g, Add(BV(16)))
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c3 = (a1 + a2)*a3
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print(c3)
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2012-01-06 18:33:28 -05:00
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c = CompositeActor(g)
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frag = c.get_control_fragment() + c.get_process_fragment()
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print(verilog.convert(frag))
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